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CS1104 – Computer Organization

CS1104 – Computer Organization

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CS1104 – Computer Organization

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  1. CS1104 – Computer Organization PART 2: Computer Architecture Lecture 7 Single-Cycle Control & Datapath Adapted from David Patterson’s CS152 course at UC Berkeley

  2. Outline • Design a processor: step-by-step • Requirements of the Instruction Set • Components and clocking • Assembling an adequate Datapath • Controlling the Datapath

  3. Processor Input Control Memory Datapath Output The Big Picture: Where are We Now? • The Five Classic Components of a Computer • Design a Single Cycle Processor

  4. CPI Inst. Count Cycle Time The Big Picture: The Performance Perspective • Performance of a machine is determined by: • Instruction count • Clock cycle time • Clock cycles per instruction • Processor design (datapath and control) will determine: • Clock cycle time • Clock cycles per instruction • Today: • Single cycle processor: • Advantage: One clock cycle per instruction • Disadvantage: long cycle time

  5. How to Design a Processor: step-by-step • 1. Analyze instruction set => datapath requirements • the meaning of each instruction is given by the register transfers • datapath must include storage element for ISA registers • possibly more • datapath must support each register transfer • 2. Select set of datapath components and establish clocking methodology • 3. Assemble datapath meeting the requirements • 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. • 5. Assemble the control logic

  6. 31 26 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 31 26 21 16 0 immediate op rs rt 6 bits 5 bits 5 bits 16 bits 31 26 0 op target address 6 bits 26 bits The MIPS Instruction Formats • All MIPS instructions are 32 bits long. The three instruction formats: • R-type • I-type • J-type • The different fields are: • op: operation of the instruction • rs, rt, rd: the source and destination register specifiers • shamt: shift amount • funct: selects the variant of the operation in the “op” field • address / immediate: address offset or immediate value • target address: target address of the jump instruction

  7. 31 26 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits Step 1a: The MIPS-lite Subset for today • ADD and SUB • addU rd, rs, rt • subU rd, rs, rt • OR Immediate: • ori rt, rs, imm16 • LOAD and STORE Word • lw rt, rs, imm16 • sw rt, rs, imm16 • BRANCH: • beq rs, rt, imm16

  8. Logical Register Transfers • RTL gives the meaning of the instructions • All start by fetching the instruction op | rs | rt | rd | shamt | funct = MEM[ PC ] op | rs | rt | Imm16 = MEM[ PC ] inst Register Transfers ADDU R[rd] <– R[rs] + R[rt]; PC <– PC + 4 SUBU R[rd] <– R[rs] – R[rt]; PC <– PC + 4 ORi R[rt] <– R[rs] + zero_ext(Imm16); PC <– PC + 4 LOAD R[rt] <– MEM[ R[rs] + sign_ext(Imm16)]; PC <– PC + 4 STORE MEM[ R[rs] + sign_ext(Imm16) ] <– R[rt]; PC <– PC + 4 BEQ if ( R[rs] == R[rt] ) then PC <– PC + sign_ext(Imm16)] || 00 else PC <– PC + 4

  9. Step 1: Requirements of the Instruction Set • Memory • instruction & data • Registers (32 x 32) • read RS • read RT • Write RT or RD • PC • Extender • Add and Sub register or extended immediate • Add 4 or extended immediate to PC

  10. Step 2: Components of the Datapath • Combinational Elements • Storage Elements • Clocking methodology

  11. Combinational Logic Elements (Basic Building Blocks) CarryIn A 32 • Adder • MUX • ALU Sum Adder 32 B Carry 32 Select A 32 Y MUX 32 B 32 OP A 32 Result ALU 32 B 32

  12. Storage Element: Register (Basic Building Block) • Register • Similar to the D Flip Flop except • N-bit input and output • Write Enable input • Write Enable: • negated (0): Data Out will not change • asserted (1): Data Out will become Data In Write Enable Data In Data Out N N Clk

  13. RW RA RB Write Enable 5 5 5 busA busW 32 32 32-bit Registers 32 busB Clk 32 Storage Element: Register File • Register File consists of 32 registers: • Two 32-bit output busses: busA and busB • One 32-bit input bus: busW • Register is selected by: • RA (number) selects the register to put on busA (data) • RB (number) selects the register to put on busB (data) • RW (number) selects the register to be writtenvia busW (data) when Write Enable is 1 • Clock input (CLK) • The CLK input is a factor ONLY during write operation • During read operation, behaves as a combinational logic block: • RA or RB valid => busA or busB valid after “access time.”

  14. Write Enable Address Data In DataOut 32 32 Clk Storage Element: Idealized Memory • Memory (idealized) • One input bus: Data In • One output bus: Data Out • Memory word is selected by: • Address selects the word to put on Data Out • Write Enable = 1: address selects the memoryword to be written via the Data In bus • Clock input (CLK) • The CLK input is a factor ONLY during write operation • During read operation, behaves as a combinational logic block: • Address valid => Data Out valid after “access time.”

  15. Clk Setup Hold Setup Hold Don’t Care . . . . . . . . . . . . Clocking Methodology • All storage elements are clocked by the same clock edge • Cycle Time = CLK-to-Q + Longest Delay Path + Setup + Clock Skew • (CLK-to-Q + Shortest Delay Path - Clock Skew) > Hold Time

  16. Step 3 • Register Transfer Requirements–> Datapath Assembly • Instruction Fetch • Read Operands and Execute Operation

  17. PC Clk Next Address Logic Address Instruction Memory 3a: Overview of the Instruction Fetch Unit • The common RTL operations • Fetch the Instruction: mem[PC] • Update the program counter: • Sequential Code: PC <- PC + 4 • Branch and Jump: PC <- “something else” Instruction Word 32

  18. 31 26 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 3b: Add & Subtract • R[rd] <- R[rs] op R[rt] Example: addU rd, rs, rt • Ra, Rb, and Rw come from instruction’s rs, rt, and rd fields • ALUctr and RegWr: control logic after decoding the instruction Rd Rs Rt ALUctr RegWr 5 5 5 busA Rw Ra Rb busW 32 32 32-bit Registers Result ALU 32 32 busB Clk 32

  19. Clk-to-Q Old Value New Value Instruction Memory Access Time Rs, Rt, Rd, Op, Func Old Value New Value Delay through Control Logic Old Value New Value Old Value New Value Register File Access Time Old Value New Value ALU Delay Old Value New Value Rd Rs Rt ALUctr Register Write Occurs Here RegWr 5 5 5 busA Rw Ra Rb busW 32 32 32-bit Registers Result ALU 32 32 busB Clk 32 Register-Register Timing Clk PC ALUctr RegWr busA, B busW

  20. 11 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits rd? 31 16 15 0 immediate 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 bits 16 bits Rd Rt RegDst Mux Rs ALUctr RegWr 5 5 5 busA Rw Ra Rb busW 32 Result 32 32-bit Registers ALU 32 32 busB Clk 32 Mux Sign Ext imm16 32 16 ALUSrc 3c: Logical Operations with Immediate • R[rt] <- R[rs] op ZeroExt[imm16] ]

  21. 11 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits rd Rd Rt RegDst Mux Rs ALUctr RegWr 5 5 5 busA W_Src Rw Ra Rb busW 32 32 32-bit Registers ALU 32 32 busB Clk MemWr 32 Mux Mux WrEn Adr Data In 32 Data Memory Extender 32 imm16 32 16 Clk ALUSrc 3d: Load Operations • R[rt] <- Mem[R[rs] + SignExt[imm16]] Example: lw rt, rs, imm16 ExtOp

  22. 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits Rd Rt ALUctr MemWr W_Src RegDst Mux Rs Rt RegWr 5 5 5 busA Rw Ra Rb busW 32 32 32-bit Registers ALU 32 32 busB Clk 32 Mux Mux WrEn Adr Data In 32 32 Data Memory Extender imm16 32 16 Clk ALUSrc ExtOp 3e: Store Operations • Mem[ R[rs] + SignExt[imm16] <- R[rt] ] Example: sw rt, rs, imm16

  23. 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits 3f: The Branch Instruction • beq rs, rt, imm16 • mem[PC] Fetch the instruction from memory • Equal <- R[rs] == R[rt] Calculate the branch condition • if (COND eq 0) Calculate the next instruction’s address • PC <- PC + 4 + ( SignExt(imm16) x 4 ) • else • PC <- PC + 4

  24. 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits Inst Address Cond nPC_sel Rs Rt 4 RegWr 5 5 5 busA 32 Adder Rw Ra Rb busW 00 32 32 32-bit Registers Equal? Mux PC busB Clk 32 Adder imm16 PC Ext Clk Datapath for Branch Operations • beq rs, rt, imm16 Datapath generates condition (equal)

  25. Instruction<31:0> Inst Memory <21:25> <16:20> <11:15> <0:15> Adr Rs Rt Rd Imm16 RegDst nPC_sel ALUctr MemWr MemtoReg Equal Rt Rd 0 1 Rs Rt 4 RegWr 5 5 5 busA Adder Rw Ra Rb = busW 00 32 32 32-bit Registers ALU 0 32 Mux busB 32 0 PC 32 Mux Mux Clk 32 Adder WrEn Adr 1 Clk 1 Data In Extender Data Memory PC Ext imm16 32 16 imm16 Clk ExtOp ALUSrc Putting it All Together: A Single Cycle Datapath

  26. Critical Path (Load Operation) = PC’s Clk-to-Q + Instruction Memory’s Access Time + Register File’s Access Time + ALU to Perform a 32-bit Add + Data Memory Access Time + Setup Time for Register File Write + Clock Skew Ideal Instruction Memory Instruction Rd Rs Rt Imm 5 5 5 16 Instruction Address A Data Address 32 Rw Ra Rb 32 Ideal Data Memory 32 32 32-bit Registers ALU PC Next Address Data In B Clk Clk 32 Clk An Abstract View of the Critical Path • Register file and ideal memory: • The CLK input is a factor ONLY during write operation • During read operation, behave as combinational logic: • Address valid => Output valid after “access time.”

  27. Instruction<31:0> Inst Memory <21:25> <21:25> <16:20> <11:15> <0:15> Adr Op Fun Rt Rs Rd Imm16 Control ALUctr nPC_sel MemWr MemtoReg ALUSrc RegWr RegDst ExtOp Equal DATA PATH Step 4: Given Datapath: RTL -> Control

  28. Inst Memory Adr nPC_sel 4 00 Adder PC Mux Clk imm16 PC Ext Adder Meaning of the Control Signals • Rs, Rt, Rd and Imed16 hardwired into datapath • nPC_sel: 0 => PC <– PC + 4; 1 => PC <– PC + 4 + SignExt(Im16) || 00

  29. RegDst ALUctr MemWr MemtoReg Equal Rt Rd 0 1 Rs Rt RegWr 5 5 5 busA = Rw Ra Rb busW 32 32 32-bit Registers ALU 0 32 busB 32 0 32 Mux Mux Clk 32 WrEn Adr 1 1 Data In Extender Data Memory imm16 32 16 Clk ExtOp ALUSrc Meaning of the Control Signals • MemWr: write memory • MemtoReg: 1 => Mem • RegDst: 0 => “rt”; 1 => “rd” • RegWr: write dest register • ExtOp: “zero”, “sign” • ALUsrc: 0 => regB; 1 => immed • ALUctr: “add”, “sub”, “or”

  30. Control Signals inst Register Transfer ADD R[rd] <– R[rs] + R[rt]; PC <– PC + 4 ALUsrc = RegB, ALUctr = “add”, RegDst = rd, RegWr, nPC_sel = “+4” SUB R[rd] <– R[rs] – R[rt]; PC <– PC + 4 ALUsrc = ___, Extop = __, ALUctr = ___, RegDst = ___, RegWr(?), MemtoReg(?), MemWr(?), nPC_sel =__ ORi R[rt] <– R[rs] + zero_ext(Imm16); PC <– PC + 4 ALUsrc = ___, Extop = __, ALUctr = ___, RegDst = ___, RegWr(?), MemtoReg(?), MemWr(?), nPC_sel =__ LOAD R[rt] <– MEM[ R[rs] + sign_ext(Imm16)]; PC <– PC + 4 ALUsrc = ___, Extop = __, ALUctr = ___, RegDst = ___, RegWr(?), MemtoReg(?), MemWr(?), nPC_sel =__ STORE MEM[ R[rs] + sign_ext(Imm16)] <– R[rs]; PC <– PC + 4 ALUsrc = ___, Extop = __, ALUctr = ___, RegDst = ___, RegWr(?), MemtoReg(?), MemWr(?), nPC_sel =__ BEQ if ( R[rs] == R[rt] ) then PC <– PC + sign_ext(Imm16)] || 00 else PC <– PC + 4 ALUsrc = ___, Extop = __, ALUctr = ___, RegDst = ___, RegWr(?), MemtoReg(?), MemWr(?), nPC_sel =__

  31. Step 5: Logic for each control signal • nPC_sel <= if (OP == BEQ) then EQUAL else 0 • ALUsrc <= if (OP == “000000”) then “regB” else “immed” • ALUctr <= if (OP == “000000”) then funct elseif (OP == ORi) then “OR” elseif (OP == BEQ) then “sub” else “add” • ExtOp <= _____________ • MemWr <= _____________ • MemtoReg <= _____________ • RegWr: <=_____________ • RegDst: <= _____________

  32. Adder Mux Adder Example: Load Instruction Instruction<31:0> Inst Memory <0:15> <11:15> <21:25> <16:20> Adr Rs Rt Rd Imm16 RegDst nPC_sel ALUctr MemWr MemtoReg Rt Equal Rd rt add +4 0 1 Rs Rt 4 RegWr 5 5 5 busA Rw Ra Rb = busW 00 32 32 32-bit Registers ALU 0 32 busB 32 0 PC 32 Mux Mux Clk 32 WrEn Adr 1 Clk 1 Data In Extender Data Memory imm16 PC Ext 32 16 imm16 Clk sign ext ExtOp ALUSrc

  33. Control Ideal Instruction Memory Control Signals Conditions Instruction Rd Rs Rt 5 5 5 Instruction Address A Data Address Data Out 32 Rw Ra Rb 32 Ideal Data Memory 32 32 32-bit Registers ALU PC Next Address Data In B Clk Clk 32 Clk Datapath An Abstract View of the Implementation • Logical vs. Physical Structure

  34. Summary till now • 5steps to design a processor • 1. Analyze instruction set => datapath requirements • 2. Select set of datapath components & establish clock methodology • 3. Assemble datapath meeting the requirements • 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. • 5. Assemble the control logic • MIPS makes it easier • Instructions same size • Source registers always in same place • Immediates same size, location • Operations always on registers/immediates • Single cycle datapath => CPI=1, CCT => long • Next: implementing control

  35. 31 26 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits RTL: The Add Instruction • add rd, rs, rt • mem[PC] Fetch the instruction from memory • R[rd] <- R[rs] + R[rt] The actual operation • PC <- PC + 4 Calculate the next instruction’s address

  36. Inst Memory Instruction<31:0> Adr nPC_sel 4 Adder 00 Mux PC Adder Clk imm16 PC Ext Instruction Fetch Unit at the Beginning of Add • Fetch the instruction from Instruction memory: Instruction <- mem[PC] • This is the same for all instructions

  37. 31 26 21 16 11 6 0 op rs rt rd shamt funct The Single Cycle Datapath during Add • R[rd] <- R[rs] + R[rt] Instruction<31:0> nPC_sel= +4 Instruction Fetch Unit <21:25> <16:20> <11:15> <0:15> Rd Rt Clk RegDst = 1 1 0 Mux ALUctr = Add Rt Rs Rd Imm16 Rs Rt RegWr = 1 5 5 5 MemtoReg = 0 busA Zero MemWr = 0 Rw Ra Rb busW 32 32 32-bit Registers 0 ALU 32 busB 32 0 Clk Mux 32 Mux 32 1 WrEn Adr 1 Data In 32 Data Memory Extender imm16 32 16 Clk ALUSrc = 0 ExtOp = x

  38. Inst Memory Adr Adder Mux Adder Instruction Fetch Unit at the End of Add • PC <- PC + 4 • This is the same for all instructions except: Branch and Jump Instruction<31:0> nPC_sel 4 00 PC Clk imm16

  39. 31 26 21 16 0 op rs rt immediate The Single Cycle Datapath during Or Immediate • R[rt] <- R[rs] or ZeroExt[Imm16] Instruction<31:0> nPC_sel = Instruction Fetch Unit <21:25> <16:20> <11:15> <0:15> Rd Rt Clk RegDst = 1 0 Mux Rt Rs Rd Imm16 Rs Rt ALUctr = RegWr = 5 5 5 MemtoReg = busA Zero MemWr = Rw Ra Rb busW 32 32 32-bit Registers 0 ALU 32 busB 32 0 Clk Mux 32 Mux 32 1 WrEn Adr 1 Data In 32 Data Memory Extender imm16 32 16 Clk ALUSrc = ExtOp =

  40. 31 26 21 16 0 op rs rt immediate The Single Cycle Datapath during Or Immediate • R[rt] <- R[rs] or ZeroExt[Imm16] Instruction<31:0> nPC_sel= +4 Instruction Fetch Unit <21:25> <16:20> <11:15> <0:15> Rd Rt Clk RegDst = 0 1 0 Mux Rt Rs Rd Imm16 Rs Rt ALUctr = Or RegWr = 1 MemtoReg = 0 5 5 5 busA Zero MemWr = 0 Rw Ra Rb busW 32 32 32-bit Registers 0 ALU 32 busB 32 0 Clk Mux 32 Mux 32 1 WrEn Adr 1 Data In 32 Data Memory Extender imm16 32 16 Clk ALUSrc = 1 ExtOp = 0

  41. 31 26 21 16 0 op rs rt immediate The Single Cycle Datapath during Load • R[rt] <- Data Memory {R[rs] + SignExt[imm16]} Instruction<31:0> nPC_sel= +4 Instruction Fetch Unit <21:25> <16:20> <11:15> <0:15> Rd Rt Clk RegDst = 0 1 0 Mux ALUctr = Add Rt Rs Rd Imm16 Rs Rt RegWr = 1 MemtoReg = 1 5 5 5 busA Zero MemWr = 0 Rw Ra Rb busW 32 32 32-bit Registers 0 ALU 32 busB 32 0 Clk Mux 32 Mux 1 WrEn Adr 1 Data In 32 Data Memory Extender 32 imm16 32 16 Clk ALUSrc = 1 ExtOp = 1

  42. 31 26 21 16 0 op rs rt immediate The Single Cycle Datapath during Store • Data Memory {R[rs] + SignExt[imm16]} <- R[rt] Instruction<31:0> nPC_sel = Instruction Fetch Unit <21:25> <16:20> <11:15> <0:15> Rd Rt Clk RegDst = 1 0 Mux Rt Rs Rd Imm16 Rs Rt ALUctr = RegWr = 5 5 5 MemtoReg = busA Zero MemWr = Rw Ra Rb busW 32 32 32-bit Registers 0 ALU 32 busB 32 0 Clk Mux 32 Mux 32 1 WrEn Adr 1 Data In 32 Data Memory Extender imm16 32 16 Clk ALUSrc = ExtOp =

  43. 31 26 21 16 0 op rs rt immediate The Single Cycle Datapath during Store • Data Memory {R[rs] + SignExt[imm16]} <- R[rt] Instruction<31:0> nPC_sel= +4 Instruction Fetch Unit <21:25> <16:20> <11:15> <0:15> Rd Rt Clk RegDst = x 1 0 Mux ALUctr = Add Rt Rs Rd Imm16 Rs Rt RegWr = 0 5 5 5 MemtoReg = x busA Zero MemWr = 1 Rw Ra Rb busW 32 32 32-bit Registers 0 ALU 32 busB 32 0 Clk Mux 32 Mux 32 1 WrEn Adr 1 32 Data In Data Memory Extender imm16 32 16 Clk ALUSrc = 1 ExtOp = 1

  44. 31 26 21 16 0 op rs rt immediate The Single Cycle Datapath during Branch • if (R[rs] - R[rt] == 0) then Zero <- 1 ; else Zero <- 0 Instruction<31:0> nPC_sel= “Br” Instruction Fetch Unit <21:25> <16:20> <11:15> <0:15> Rd Rt Clk RegDst = x 1 0 Mux ALUctr = Subtract Rt Rs Rd Imm16 Rs Rt RegWr = 0 MemtoReg = x 5 5 5 busA Zero MemWr = 0 Rw Ra Rb busW 32 32 32-bit Registers 0 ALU 32 busB 32 0 Clk Mux 32 Mux 32 1 WrEn Adr 1 Data In 32 Data Memory Extender imm16 32 16 Clk ALUSrc = 0 ExtOp = x

  45. 31 26 21 16 0 op rs rt immediate Inst Memory Instruction<31:0> Adr nPC_sel 4 Adder 00 Mux PC Adder Clk imm16 Instruction Fetch Unit at the End of Branch • if (Zero == 1) then PC = PC + 4 + SignExt[imm16]*4 ; else PC = PC + 4

  46. Step 4: Given Datapath: RTL -> Control Instruction<31:0> Inst Memory <21:25> <21:25> <16:20> <11:15> <0:15> Adr Op Fun Rt Rs Rd Imm16 Control ALUctr nPC_sel MemWr MemtoReg ALUSrc RegWr RegDst ExtOp Equal DATA PATH

  47. A Summary of Control Signals inst Register Transfer ADD R[rd] <– R[rs] + R[rt]; PC <– PC + 4 ALUsrc = RegB, ALUctr = “add”, RegDst = rd, RegWr, nPC_sel = “+4” SUB R[rd] <– R[rs] – R[rt]; PC <– PC + 4 ALUsrc = RegB, ALUctr = “sub”, RegDst = rd, RegWr, nPC_sel = “+4” ORi R[rt] <– R[rs] + zero_ext(Imm16); PC <– PC + 4 ALUsrc = Im, Extop = “Z”, ALUctr = “or”, RegDst = rt, RegWr, nPC_sel = “+4” LOAD R[rt] <– MEM[ R[rs] + sign_ext(Imm16)]; PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemtoReg, RegDst = rt, RegWr, nPC_sel = “+4” STORE MEM[ R[rs] + sign_ext(Imm16)] <– R[rs]; PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemWr, nPC_sel = “+4” BEQ if ( R[rs] == R[rt] ) then PC <– PC + sign_ext(Imm16)] || 00 else PC <– PC + 4 nPC_sel = “Br”, ALUctr = “sub”

  48. add sub ori lw sw beq jump RegDst 1 1 0 0 x x x ALUSrc 0 0 1 1 1 0 x MemtoReg 0 0 0 1 x x x RegWrite 1 1 1 1 0 0 0 MemWrite 0 0 0 0 1 0 0 nPCsel 0 0 0 0 0 1 0 Jump 0 0 0 0 0 0 1 ExtOp x x 0 1 1 x x ALUctr<2:0> Add Subtract Or Add Add xxx Subtract 31 26 21 16 11 6 0 op rs rt rd shamt funct immediate op rs rt op target address A Summary of the Control Signals Follows from the coding in MIPS func 10 0000 10 0010 We Don’t Care :-) op 00 0000 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010 R-type add, sub I-type ori, lw, sw, beq J-type jump

  49. op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010 R-type ori lw sw beq jump RegDst 1 0 0 x x x ALUSrc 0 1 1 1 0 x MemtoReg 0 0 1 x x x RegWrite 1 1 1 0 0 0 MemWrite 0 0 0 1 0 0 Branch 0 0 0 0 1 0 Jump 0 0 0 0 0 1 ExtOp x 0 1 1 x x ALUop<N:0> “R-type” Or Add Add xxx Subtract func ALUctr ALU Control (Local) op 6 Main Control 3 ALUop 6 N ALU The Concept of Local Decoding

  50. func ALU Control (Local) op 6 ALUctr Main Control ALUop 6 3 N The Encoding of ALUop • In this exercise, ALUop has to be 2 bits wide to represent: • (1) “R-type” instructions • “I-type” instructions that require the ALU to perform: • (2) Or, (3) Add, and (4) Subtract • To implement the full MIPS ISA, ALUop has to be 3 bits to represent: • (1) “R-type” instructions • “I-type” instructions that require the ALU to perform: • (2) Or, (3) Add, (4) Subtract, and (5) And (Example: andi) R-type ori lw sw beq jump ALUop (Symbolic) “R-type” Or Add Add xxx Subtract ALUop 1 00 0 10 0 00 0 00 xxx 0 01