A look at interrupts

1. A look at interrupts What are interrupts and why are they needed

2. The “standard” instruction cycle DECODE THE INSTRUCTION AND FETCH ANY VALUES NEEDED FROM REGISTER OR MEMORY RESETTHE PROCESSOR RESET*INTERRUPT(ACTIVE low) FETCH AN INSTRUCTION FROM PROGRAM MEMORY WRITE BACK THE ANSWER EXECUTE THE INSTRUCTION PROCESSOR RESET* +5V +5V RC time constant200 ms on68K GROUND

3. The “standard” instruction cycle DECODE THE INSTRUCTION AND FETCH ANY VALUES NEEDED FROM REGISTER OR MEMORY RESETTHE PROCESSOR RESET*(ACTIVE low) FETCH AN INSTRUCTION FROM PROGRAM MEMORY WRITE BACK THE ANSWER EXECUTE THE INSTRUCTION EXECUTING‘YOUR PROGRAM’ UNTIL POWER IS REMOVED

4. The “standard” instruction cycle DECODE THE INSTRUCTION AND FETCH ANY VALUES NEEDED FROM REGISTER OR MEMORY RESETTHE PROCESSOR RESET*(ACTIVE low) FETCH AN INSTRUCTION FROM PROGRAM MEMORY WRITE BACK THE ANSWER EXECUTE THE INSTRUCTION This is the data 16-bits EXTERNAL HARDWARE Control signal – ThanksData received Control signal – I have data for you

5. The “wait till ready approach In decode phase – read control register value In execute phase – check if 1 -- keep waiting (fetch-decode-execute-writeback) until the control value is 1 When 1 – go to a different part of your program code to read the data – then your program must send an acknowledge back to device that the data has been read. The device can then go and get more values for you. PROBLEM: You have no time to do anything else Not a problem if waiting for this device is the only thing you want to do with the processor

6. Wait till ready approachVery problematic if many devices DECODE THE INSTRUCTION AND FETCH ANY VALUES NEEDED FROM REGISTER OR MEMORY RESETTHE PROCESSOR RESET*(ACTIVE low) FETCH AN INSTRUCTION FROM PROGRAM MEMORY WRITE BACK THE ANSWER EXECUTE THE INSTRUCTION 16-bits 16-bits EXTERNAL HARDWARE EXTERNAL HARDWARE 16-bits EXTERNAL HARDWARE

7. The “Poll approach”Not much waiting – but a lot of “doing” read control register value of device 1 -- if 1 go to a different part of the code to “read the data” – after reading the data send an acknowledge signal back to device 1 -- if 0 go and read the control value of device 2 – don’t worry about device 1 for some time read control register value of device 2 -- if 1 go to a different part of the code to “read the data” – after reading the data send an acknowledge signal back to device 2 -- if 0 go and read the control value of device 3 – don’t worry about device 2 and 3 for some time ETC PROBLEM: What happens if, while you are handling device 2, device 1 has “time sensitive information” that will disappear if device 1 is not serviced immediately

8. Interrupt Approach – basic idea DECODE THE INSTRUCTION AND FETCH ANY VALUES NEEDED FROM REGISTER OR MEMORY RESETTHE PROCESSOR RESET*(ACTIVE low) FETCH AN INSTRUCTION FROM “NORMAL”(NOT ISR) PROGRAM MEMORY NO CONTINUEAS BEFORE CHECK IF ANINTERRUPT REQUEST HAS OCCURRED EXECUTE THE INSTRUCTION WRITE BACK THE ANSWER yes DOISR 16-bits CONTROL SIGNALDATA READY SIGNAL Acknowledge done EXTERNAL HARDWARE

9. Issues to solve • What if hardware can only provide a “quick” I am ready signal? • What if more than one hardware wants to send an interrupt? • What if the programmer wants to “ignore” a “low priority” interrupt? • What if certain interrupts are too important to ignore?

10. What if hardware can only provide a “quick” I am ready signal? CONTINUEAS BEFORE CHECK IF ANINTERRUPT REQUEST HAS OCCURRED DOISR yes Interrupt Latch (Capture) Processorclock signal causes loadof the latch to capturethe transient interrupt Interrupt Buffer 16-bits CONTROL SIGNALDATA READY SIGNAL Acknowledge done EXTERNAL HARDWARE

11. What if the programmer wants to “ignore” a “low priority” interrupt? CONTINUEAS BEFORE CHECK IF ANINTERRUPT REQUEST HAS OCCURRED Interrupt Latch (Capture) DOISR yes Interrupt MaskIgnore Processorclock signal causes loadof the latch to capturethe transient interrupt Interrupt Buffer 16-bits CONTROL SIGNALDATA READY SIGNAL Acknowledge done EXTERNAL HARDWARE

12. What if certain hardware interrupts are too important to ignore? CONTINUEAS BEFORE CHECK IF ANINTERRUPT REQUEST HAS OCCURRED Interrupt Latch (Capture) DOISR yes Interrupt MaskIgnore Processorclock signal causes loadof the latch to capturethe transient interrupt Interrupt Buffer 16-bits CONTROL SIGNALDATA READY SIGNAL Acknowledge done EXTERNAL HARDWARE

13. What if more than one hardware wants to send an interrupt? Pending interrupts(to be done CONTINUEAS BEFORE CHECK IF ANINTERRUPT REQUEST HAS OCCURRED Interrupt Latch (Capture) DOISR yes Interrupt MaskIgnore Processorclock signal causes loadof the latch to capturethe transient interrupt Interrupt Buffer 16-bits CONTROL SIGNALDATA READY SIGNAL Acknowledge done EXTERNAL HARDWARE

14. Blackfin MASKS and Latches

16. Normal “linear flow”PC increments to next instruction Use program counter PC as an Instruction Pointer registerFetch instruction at memory locationPC then increment the PC to point atthe next instruction PC = PC+2 PC = PC + 4;

17. Subroutine call flow PC = PC + 2 CALL MEANSRETS = PC + 4 (FFA03C78) PC = 0xFFA01E24 This instruction is NOT fetched (until end of subroutine) This instruction is now fetchedHAVE JUMPED TO SUBROUTINE

18. Interrupt occurs HEREMust Jump to ISR NOW– but how? Use program counter PC as an Instruction Pointer registerFetch instruction at memory locationPC then increment the PC to point atthe next instruction PC = PC+2 PC = PC + 4;

19. First step is obvious PC has 0xFFA01E44 in it – Just about to fetch P0.L = instruction Remember what instruction you were about to execute – so you can do that instruction after finishing the ISR RETI = PC (0xFFA01E44) PC = ????? Interrupt occurs HEREMust Jump to ISR NOW – but how?

20. First step is obvious Remember what instruction you were about to execute RETI = PC (0xFFA01E44) PC = ????? Some how – like magic must make PC = start of Timer ISR0xFFA01EC0 Interrupt occurs HEREMust Jump to ISR – but how

21. Solution – Lookup tableof what value to put into PC for what interrupt • Same idea as for my answer for Q3 in Post Lab Quiz 1 – Except that the hardware is reading the value from the table and not the program Event (e.g interrupts) Table

22. Why are all these “event addresses” in the jump table the same? This is the address of the “the processor does not know what to do if there is an interrupt of this sort” EXCEPTION

23. The unknown “exception”interrupt service routine • IDLE This is theassembly code While(wait till some happens) instruction VDSP Emulator puts in a “breakpoint” so for us the program stops. In real life – processor can’t “stop”, just goes into an infiniteloop until “watchdog timer” resets the processor

24. Solution – Lookup tableof what value to put into PC for what interrupt • Question – the start of the ISR is in the event table – How did it get there? Event (e.g interrupts) Table

25. The start address of the ISR got into the event table HOW? • It got there because we told C++ to put it there for us Also we can understand what the raise( ) C++ function does

26. Blackfin MASKS and Latches Raise( ) use “software to put a 1 into the interrupt latch register – making the processorthink that a hardware interrupt has happened

27. Event table information can be found in the Blackfin Hardware Manual

28. What happens if the device does take away its “I’m ready” signal during an interrupt? CONTINUEAS BEFORE CHECK IF ANINTERRUPT REQUEST HAS OCCURRED DOISR yes Interrupt Latch (Capture) Processorclock signal causes loadof the latch to capturethe transient interrupt Interrupt Buffer 16-bits CONTROL SIGNALDATA READY SIGNAL Acknowledge done EXTERNAL HARDWARE

29. Tackled today • Three ways of handling hardware requests for service • Wait till the device signals “ready”then process the data • If device 1 ready – process its data • If device 2 ready – process its data • Interrupt – start processing the data from a “specific device NOW!