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Interfacing with I/O Devices

Interfacing with I/O Devices. Overview. Memory mapped vs programmatic I/O Organization of a memory mapped I/O device Polled I/O Interrupt-driven I/O ISR’s Shared IRQ’s Vectored interrupts. CPU. Memory. I/O. I/O Device Models. Programmed I/O

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Interfacing with I/O Devices

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  1. Interfacing with I/O Devices

  2. Overview • Memory mapped vs programmatic I/O • Organization of a memory mapped I/O device • Polled I/O • Interrupt-driven I/O • ISR’s • Shared IRQ’s • Vectored interrupts Interfacing with I/O devices

  3. CPU Memory I/O I/O Device Models • Programmed I/O • Special instructions to read and write from I/O devices • Memory-mapped I/O • I/O devices live at memory addresses • For example: MOVE.B $8000,D0 might get a byte from an I/O device and not memory. Interfacing with I/O devices

  4. I/O Models for Common Processors • MC68000 – Memory mapped. • Intel CPUs – Programmed I/O • Separate instructions for I/O read/writes • Can also memory-map some devices • PowerPC – Memory mapped, but uses a separate address space • A special control register controls which address space is being accessed. Interfacing with I/O devices

  5. Organization of an I/O device • Base memory location • Jumpers, PnP, etc. • Status register • Sin – A word is waiting in the input register • Sout – The device is ready for output • The device knows when a register is written to or read from Device Controller $8000 Input register $8002 Output register $8004 Status register 0 1 Sout Sin Device Interfacing with I/O devices

  6. Polled I/O • New instruction: BTST.L #bit,Dn • Set Z according to bit of register Dn • BEQ will branch if bit = 0, BNE if bit = 1 GETCH LEA BUFFER,A0 POLLI MOVE.B $8004,D0 BTST.B #0,D0 BEQ POLLI MOVE.B $8000,(A0)+ PUTCH MOVE.B $8004,D1 BTST.B #1,D1 BEQ PUTCH MOVE.B D0,$8002 Device Controller Input register $8000 Output register $8002 $8004 Status reg. 0 1 Sout Sin Device Interfacing with I/O devices

  7. Drawbacks of Polled I/O • The CPU can’t do anything else while it is polling. • You must explicitly check every device in the system. • How often should you check the modem to see if there is a ring? • No way for devices to get the attention of the CPU until it is their “turn”. • No way to assure fast response to external events. Interfacing with I/O devices

  8. CPU Memory I/O Interrupt-driven I/O • When IRQ goes active, jump to a special memory location: the ISR, or interrupt service routine. • Activate IACK to tell the device that the interrupt is being serviced, and it can stop activating the IRQ line. IRQ IACK Interfacing with I/O devices

  9. CPU MEM I/O An ISR for a keyboard driver KBINIT MOVE.L #KBUF,KBPTR RTS KBISR MOVEM.L D0/A0-A1,-(SP) MOVEA.L KBPTR,A0 MOVE.B $8000,D0 CMPI.B #$0D,D0 ; CR? BEQ PROC_INPUT MOVEA.L A0,A1 SUBA.L #KBUF,A1 CMPA.L #KBSIZE,A1 BGE KB_OVERFLOW MOVE.B D0,(A0)+ MOVEA.L A0,KBPTR DONE MOVEM.L (SP)+,D0/A0-A1 RTE ; a new instr KBSIZE EQU 132 KBUF DS.B KBSIZE KBPTR DS.L 1 IRQ IACK Device Controller $8000 Input register $8002 Output register $8004 Status reg 0 1 Sout Sin Interfacing with I/O devices

  10. ISR’s: Even more transparent • May be called at any time. • Must be completely invisible to the current running program. • Must save all register values & restore them. • Some systems do this in hardware, some rely on the ISR to take care of it. The 68000 splits up the work… • The SR and the PC are saved when an INTR is triggered • The ISR must save and restore any other registers used • The RTE instruction restores the SR and the PC Interfacing with I/O devices

  11. What happens on an interrupt • SR: • When an interrupt is activated, the CPU: • Pushes the PC (L) and the SR (W) on the stack • Switches to supervisor mode (S=1) • Jumps to the ISR • In supervisor mode, we can write to the status register and use the supervisor stack! T S I I I X N Z V C Trace Interruptpriority Conditioncodes Supervisor Interfacing with I/O devices

  12. The RTE instruction • When the ISR is done servicing the interrupt, it returns using the RTE (return from exception) instruction. • This instruction is similar to RTS, but it does more. RTE does the following: • SR  [[SP]] • SP  [SP] + 2 • PC  [[SP]] • SP  [SP] + 4 This will restore the S bit along with the rest of the SR.If we were in user mode, before the interrupt, we are back in user mode when we return from the ISR. Interfacing with I/O devices

  13. Interrupts from multiple devices • When IRQ is activated, the CPU checks bit I in the status register of each device to see which one (or more) need an IRQ serviced. • The order is fixed, so the first device polled has higher de facto priority Bus CPU Memory I/O 1 I/O 2 I/O 3 I/O 4 IRQ Device Controller Input register Output register 1 0 1 I Sout Sin Interfacing with I/O devices

  14. Vectored Interrupts • If we have multiple devices, we need a very large ISR that knows how to deal with all of them! • Using vectored interrupts, we can have a different ISR for each device. • Each I/O device has a special register where it keeps a special number called the interrupt vector. • The vector tells the CPU where to look for the ISR. Interfacing with I/O devices

  15. A vectored-interrupt device Device Controller $8000 Input register … Sin Sout $8002 Output register IESIN IESOUT $8004 Status register $8006 Interrupt VectorRegister 67 • When I trigger an interrupt, look up address number 67 in the vector table, and jump to that address. Interfacing with I/O devices

  16. Getting the interrupt vector • INTA tells a device to put the interrupt vector on the bus • INTA is daisy chained so only one device will respond INTA Memory CPU I/O 1 I/O 2 I/O 3 I/O 4 IRQ Interfacing with I/O devices

  17. The Vector Table • The interrupt vector table is stored in memory addresses $0000 through $03FC. • The contents of the vector table are addresses to jump to when each vectored interrupt occurs. (Absolute long) $0000 0 – Reset SP $0004 1 – Reset PC $0008 2 – Access Fault $000C 3 – Address Err $0010 4 – Illegal Instr $0014 5 – Div by zero … … $0100 64 – 255 user defined… … $03FC Interfacing with I/O devices

  18. The 68000 Vector table • Each entry in the vector table is the address of an ISR. • Each entry takes 2 words, so the location of vector n is address(n× 4) When we doTRAP #14we jump to the address stored here! Interfacing with I/O devices

  19. Installing a vectored interrupt device • Step 1: Write an ISR and store it in memory. • The ISR must know the addresses of the registers in the device • Step 2: Put the address of the ISR somewhere in the vector table • Step 3: Put the vector number in the Vector Register of the device KBISR LEA BUFFER,A0 MOVE.B $8000,D0 CMPI.B #0D,D0 ; CR? BEQ PROCESS MOVE.B D0,(A0)+ … RTE MOVE.L #KBISR, $100 ;$100 = 256 = 64 * 4 MOVE.L #64, $8006 ;$8006 = Vect. Reg. Interfacing with I/O devices

  20. Memory map for a vectored interrupt device (256) $0100 $0000 1000 $1000 ISR code … RTE … Input register $8000 $8002 Output register Status register $8004 $8006 64 Interfacing with I/O devices

  21. A simple keyboard driver DATAIN EQU $8000 DATAOUT EQU $8002 STATUS EQU $8004 VECTOR EQU $8006 LINE DS.B 81 PNTR DS.L 1 MOVE.L #26, VECTOR ; 26 x 4 = 104 = $68 $8000 Input register $8002 Ouptut register $8004 Status register $8006 Ivec = 26 Interfacing with I/O devices

  22. Priority Interrupts Only! • What do we do if we are processing an interrupt and another device signals an interrupt? • We can disable (mask) all interrupts while processing an interrupt (IE bit in the SR) • Some devices require very low interrupt latency (e.g. system clock) while some can tolerate long latency (e.g. keyboard). • The 68000 has 8 interrupt priorities. • While processing an interrupt of level n, interrupts from other devices of level n and lower are ignored. Only higher priority interrupts are allowed. Interfacing with I/O devices

  23. Interrupt Priorities T S I I I X N Z V C Trace Interruptpriority Conditioncodes Supervisor • An ISR can set the interrupt mask (or interrupt priority bits) by directly changing the contents of the status register. • MOVE.W xx,SR is a privileged instruction. Which means it is only allowed in supervisor mode. • 68000: An interrupt at level 7 is always accepted • A level 7 interrupt is a nonmaskable interrupt. Interfacing with I/O devices

  24. Software interrupts • Interrupts can be triggered by more than just I/O devices: • Program errors, like division by zero, can trigger interrupts. • The OS uses interrupts for multitasking and other purposes. • 68000: The TRAP instruction triggers a software interrupt • You can assign any ISR you wish to the vector entries for TRAP #0 through TRAP #15 Interfacing with I/O devices

  25. Direct Memory Access (DMA) • Even with interrupts, a lot of CPU effort is expended just moving bytes around from I/O devices to/from memory • Modem – interrupt every time a byte arrives? • DMA allows devices to access memory directly • A large amount of data can be stored to a memory location, and then an interrupt can be triggered to process all the data at once. Interfacing with I/O devices

  26. R/W A DMA Controller • A DMA controller can transfer a large amount of data between a device and memory • Example – send a stream of print data to a printer, and notify the CPU when done • The controller needs to know: • Where in memory should the data be found/put? • How many bytes of data should be transferred? Starting address Byte count Status and control register: Done IRQ IE Printer Disk Bus CPU Memory Interfacing with I/O devices

  27. Bus Arbitration • Both the CPU and the DMA controller can use the bus • There are often multiple DMA controllers • No two devices can use the bus at the same time DMA Controller CPU Printer Disk Bus Memory Interfacing with I/O devices

  28. Bus Arbitration Details BBSY • Signal Bus Request (BR) to request the bus • CPU asserts Bus Granted (BG) • If DMA controller didn’t request the bus, pass it on to BG2, BG3, etc. • Controller asserts Bus Busy (BBSY) until done CPU BR DMAController1 DMAController2 BG1 BG2 Interfacing with I/O devices

  29. Bus Arbitration Policies • No one can use the bus (not even the CPU) while BBSY is asserted, except for the DMA controller that is the current “bus master”. • Cycle stealing – When you get the bus, perform a few transfers and then release it • High-speed peripherals, like disks, get bus priority • Block mode – Perform an entire transfer before releasing the bus. Interfacing with I/O devices

  30. You should know… • General concepts for I/O devices: • Programmatic vs. memory-mapped I/O • Polling vs. Interrupt-driven I/O • Vectored interrupts, interrupt priorities • DMA, Bus Arbitration • Details for the 68000 • Exactly what happens in the CPU on an interrupt • What does the RTE instruction do? • How to write a simple ISR • How to initialize the I/O device and the vector table Interfacing with I/O devices

  31. 68000 Pinouts Interfacing with I/O devices

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