memory interface n.
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Memory interface

Memory interface

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Memory interface

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  1. Memory is a device to store data To interfacing with memories, there must be: address bus, data bus and control (chip enable, output enable) To study memory interface, we must learn how to connect memory chips to the microprocessor and how to write/read data from the memory Different kinds of memory chips will also be introduced Memory interface

  2. Memory • Knowing memory is becoming more important • Your mobile devices do not have a harddisk but they have memory • IPad or other tablet computer has no harddisk! • But still very powerful! • Latest trend SSD (solid state drive) – a data storage device that uses solid-state memory to store data similar to a traditional harddisk • SSD is now rather expensive • A 64GB SSD is in the range HKD1000

  3. Block diagram of a memory interface Address in Hex Content FFFF Data Control signals Include enable (chip select) , read/write 0000

  4. Self-test

  5. Introduction • For the 8086 microprocessor, there are two modes: minimum and maximum • Under different modes, the memory interface is not the same • In the minimum mode, 8086 processor is connected to the external memory block directly • In the maximum mode, a Bus controller is needed • The bus controller will issue the required control signal to drive the memory block

  6. Minimum Mode ALE memory 8086 /BHE /RD /WR M/IO DT//R /DEN A16-A19 AD0-AD15

  7. Address space and data organization • Memory is organized as 8-bit bytes (byte as the basic unit) • To address a word then 2 consecutive bytes are used, lower addressed byte is the LSB (Least Significant Byte) and the higher-addressed byte is the MSB (Most Significant Byte) • Words of data can be stored at even, or odd address boundaries 16-bit MSB LSB

  8. Memory addressing • The address bit A0 of the LSBcan be used to determine the address boundary. If A0 is 0 then we have an even address, or aligned • If A0 is odd then we have odd-boundary • Example: 0001H is an odd-boundary address

  9. Example • A0 = 1 example • A 16-bit data store at 01FFFH (then it is not aligned) and will occupy 01FFFH and 02000H (Odd boundary) • A0 = 0 example • A 16-bit data store at 02002H (then it is aligned) and will occupy 02002H and 02003H (even boundary)

  10. Question • If you are asked to implement the memory system for a 8086 microprocessor, what memory configuration will you use? • One 1M Bytes chip • Two 512KBytes chips • One 1M Word chip

  11. Address Space • Even-boundary data can be accessed in one bus cycle • Odd-boundary word must be accessed in two bus cycle • In 8086, user’s data usually is in 8-bit or 16-bit format • For the system, instructions are always accessed as words (16-bit) • There is also double word format (32-bit)

  12. Data type • Double word (32-bit) will be stored in 4 consecutive locations • When double word is used? • Double word can be used as a pointer that is used to address data or code outside the current segment • For a double word, the higher WORD stores the segment address, the lower WORD stores the offset

  13. Memory organization 1M bytes memory using 2 512K byte chips Odd boundary Address requires 2 cycles BHE – bank high enable

  14. Hardware organization • In hardware, the 1M bytes memory is implemented as two independent 512K-byte banks • Low (even) bank, and the high (odd) bank • Data from low bank use data bus 0-7 • Data from high bank use data bus 8-15 • Signal A0 enables the low bank • Signal /BHE enables the high bank • /BHE is active low • How many address lines are required in order to access 512K locations? (Ans. 19)

  15. Memory organization Only A1 to A19 are used to drive the memory !!! High bank Low bank

  16. Odd-addressed word transfer Need two cycles! Odd address such as 1233H (low byte) + 1234H (high byte)

  17. Example • Consider the 16-bit word stored at 01FFFH then it occupy 01FFFH and 02000H • In the first cycle data in 01FFFH will be read • In the second cycle data in 02000H will be read • Second case data stored in 02002H then data occupy 02002H and 02003H. Compare the bit pattern for 02002H and 02003H • 02002H – 0000 0010 0000 0000 0010 • 02003H – 0000 0010 0000 0000 0011 • Why both byte can be read in a single cycle?

  18. Dedicated Memory locations Dedicated memory locations should not be used as general memory space for data and program storage For the 8086, address 00000 to 0007F and FFFF0 to FFFFB are dedicated Address from FFFFC to FFFFF are reserved

  19. Exercise Determine the values for A0 and /BHE in order to access A byte at even address (/A0=0, /BHE = 1) A byte at odd address (/A0=1, /BHE = 0) A word at even address (aligned) (/A0=0, /BHE=0) A word at odd address (unaligned), as shown in the following figure (two cycles: First cycle get LSB /A0=1 /BHE=0 Second cycle get MSB /A0=0 /BHE =1 )

  20. Memory control signals • To control the memory system in the minimum mode, requires: ALE, /BHE, M/IO, DT/R, /RD, /WR, and /DEN • ALE – address latch enable, signals external circuitry that a valid address is on the bus (0->1) so the address can be stored in the latch (or buffer) • M/IO – identify whether it is a memory or IO (Input/Output) operation (high – memory, low – I/O) • DT/R – transmit or receive (1 – transmit) • DEN – to enable the data bus

  21. Read cycle of 8086 • Consists of 4 time states • T1 – memory address is on the address bus, /BHE is also output, ALE is enable • Address is latch to external device at the trailing edge of ALE • T2 – M/IO and DT/R are set to 1 and 0 respectively. These signals remain their status during the cycle • Late in T2 - /RD is switched to 0 and /DEN also set to 0

  22. Read cycle • T3 and T4 – status bits S3, S4 are output • Data are read during T3 • /RD and /DEN return to 1 at T4

  23. Read Cycle

  24. Write cycle • T1 – address and /BHE are output and latched with ALE pulse • M/IO is set to 1, DT/R is also set to 1 • T2 - /WR set to 0 and data put on data bus • Data remain in the data bus until /WR returns to 1 • When /WR returns to 1 at T4, data is written into memory

  25. Write Cycle

  26. Example • What is the duration of the bus cycle in the 8086-based microcomputer if the clock is 8MHz and two wait states are inserted Ans. 750ns (6 cycles) where each clock is 125ns

  27. Demultiplexing the address/data bus • Address and data must be available at the same time when data are to be transferred over the bus • Address and data must be separated using external demultiplexing circuits (eg a latch, or buffer) • Address are latched into external circuits by ALE (address latch enable ) at T1

  28. Demultiplexing the system bus One direction Bi-direction STB - Strobe Latches/buffers

  29. Syntax to describe a memory • Memory is usually described by its size of storage and number of data bits • Eg. A 32K bytes memory chip is represented by 32Kx8 • A 32K bits memory is represented by 32Kx1

  30. Configurations of memory for 16-bit data Chip enable (CE) usually generated by some decoding mechanism OE – output enable

  31. Simple maths • From 00000H to FFFFFH there are 1M memory locations • How about from 0000H to FFFFH? • How many locations between 1FFFFFH to 310000H (answer in terms of M + K and Byte) • A memory system has 4M locations and the starting address is 420000H what is the ending address?

  32. Memory • Read only memory (ROM) – nonvolatile • Data remains when power is turned off, data are written into the ROM during its fabrication at the factory • PROM- Programmable ROM. Can be programmed by user but this can only be done once • EPROM – erasable programmable ROM • Contents of EPROM can be erased by exposing it to ultraviolet light • EEPROM – Electrical Erasable PROM (your USB memory stick)

  33. Exercise • There is a BIOS in your computer, what kind of memory is it?

  34. Block diagram of a ROM ROM interface – address input, data output, /CE – chip enable, /OE – output enable (for READ operation)

  35. Memory Read Operation • To read a ROM, we need to issue the proper address • There is a delay between address inputs and data outputs • The access time (tACC), chip enable time (tCE), and chip deselect time (tDF) are important timing properties • You need these information for developing a real computer system

  36. Timing parameters • The access time – delay occurs before data stored at the addressed location are stable at the outputs (ie how long it takes to access data). The microprocessor must wait for tACC before reading the data

  37. ROM read operation • Access time is regarded as address to output delay. Typical value is 250ns • tCE – represents the Chip Enable to output delay, usually this is equal to access time • Deselect time – amount of time the device takes for data outputs to return to high-Z state after /OE becomes inactive

  38. Read operation tAA=access time tCO= chip select to output delay tHZ = deselect to output float

  39. Question • A normal 8086 read cycle takes 4 clocks • For a system with a 8MHz clock • Now you are required to develop the memory system for the computer which of the following devices will you use? • Tacc = 0.125us $100 • Tacc = 0.2us $50 • Tacc = 0.4us $20

  40. Choosing the proper memory

  41. Configuration of ROM for 8-bit bus How the circuit operates?

  42. EEPROM – electrical Erasable ROM • Data stored in an EEPROM can be erased electrically • Example inside the AduC832 (or 8051) microcontroller, there are 64KBytes of EEPROM

  43. Programming the EPROM • In an erased EPROM, all cells hold logic 1 • Vpp is in logic 1 for data to be read from EPROM • Vpp is ON (eg Vpp = 25V for 2716 EPROM) for programming mode (writing) • 2716 is a 2Kx8 EPROM • To write data to the EPROM a 25V signal is needed so an external device is necessary

  44. Modern EEPROM Charges in the floating gate represent the data


  46. Random access memory (RAM) • Data can be read as well as written into the memory chip • Static ram (SRAM) – data remains valid as long as the power is ON • Dynamic RAM (DRAM) – needs to periodically restore (recharge) the data in each storage location by addressing them • If storage nodes are not recharged at regular intervals of time, data would be lost. This process is called refreshing

  47. SRAM circuit To control RAM: CE – chip enable OE – output enable (for read operation) WE – write enable (for write operation) From decoding logic

  48. Write-cycle for SRAM • To write, we must produce the signal in proper order • Minimum duration of a write cycle is tWC (write cycle time ) • Address must remain stable during the whole cycle • Chip enable (CE) signal becomes active • The Write Enable (WE) will be active after the address setup time tAS elapses

  49. RAM write operation • Data should now ready and must be valid for tDW (data valid to end of write) • Data should remain valid (tDH) after the write • A short recovery period (tWR) takes place after /WE returns to 1 before the write cycle is complete (address is removed)

  50. Write cycle