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Stream Processor Simulator

Stream Processor Simulator. Ben Gaudette Michael Pfeister CSE 520 Spring 2010. Project Description. Background Stream Processing is a paradigm that exploits parallel processing via data parallelism

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Stream Processor Simulator

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  1. Stream Processor Simulator Ben Gaudette Michael Pfeister CSE 520 Spring 2010

  2. Project Description • Background • Stream Processing is a paradigm that exploits parallel processing via data parallelism • Stream Processors include GPU’s, PPU’s, Cell Processor (with software support), and the Imagine/Storm-1. • Project Goal • Create a simulator for a Stream Processor based on the Imagine.

  3. Imagine Processor - History • Originally an academic based project. • Lead by William Dally of Stanford • Created Isim • Students took all of the deliverables away and created a start up company: SPI • http://www.streamprocessors.com/

  4. Imagine Processor - Resources • The VLSI Implementation and Evaluation of Area- and Energy-Efficient Streaming Media Processors by BrucekKhailany • http://cva.stanford.edu/publications/2003/khailany_diss_onesided.pdf • Imagine Programming System User’s Guide by Peter Mattson. • http://cva.stanford.edu/classes/ee482s/docs/ips_user.pdf • Imagine Home Page • http://cva.stanford.edu/projects/imagine/

  5. Imagine Processor - Architecture

  6. Imagine Processor – ALU Cluster • 3 ADD units, 2 MUL, 1 DSQ, 1 SP, 1 COMM • Each input has a 16 word Local Register File • An Intracluster Switch is used to connect all FU outputs to all LRF’s.

  7. Imagine Processor – “our” ALU Cluster • 3 ADD units, 2 MUL, 1 DSQ • Each FU has a 32 word Local Register File • A perfect Intracluster Switch is used to connect all FU ouputs to all LRF’s.

  8. Imagine Processor – ADD FU • ADD unit is fully pipelined to 4 stages • Instructions: • FADD/FSUB – 4 cycles • ADD/SUB – 2 cycles • ILT/ILEFLT/FLE – 2 cycles • IEQ/NEQ – 1 cycle • AND/OR/XOR/NOT – 1 cycle • FTOI – 3 cycles • ITOF – 4 cycles

  9. Imagine Processor – MUL FU • MUL unit is fully pipelined to 4 stages • Instructions: • FMUL – 4 cycles • IMUL – 4 cycles • UMUL – 4 cycles

  10. Imagine Processor – DSQ FU • DSQ unit is not pipelined • Instructions: • FDIV – 17 cycles • FSQRT – 16 cycles • IDIV/UDIV – 22 cycles • IDIVR/UDIVR – 23 cycles

  11. Imagine Processor – SP & COMM FU • COMM unit • Exchanges data between clusters when a stream is not completely data parallel. • SP unit • 256 Word Scratchpad • One Read Port • One Write Port

  12. Imagine Processor – SRF

  13. Imagine Processor – Microcontroller

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