Tera-Pixel APS for CALICE

Tera-Pixel APS for CALICE Progress Meeting 6th September 2006

Main Activities • Meeting with Foundry B • Tender for 0.18 micron fabrication • Phone meeting with Foundry D • [JC] Digital logic design & simulations • [RT] New analog pixel circuits • Meeting with Guilio, Mike, Marcel & Konstantin This presentation

A B C D Bidirectional SRAM Shift-Register Cell ‘1’ Ф2b dmy dmy bck fwd Ф1 Ф2 Ф2 fwd bck ‘0’’1’

Hit Detect + Mux Consolidated Hit Logic TimeStamp DataCode DataValid Done Fwd For each reg… Phi1 RdEn# Phi2 SRAM WrEn# Mode Init ReadEn phi2 phi1 Addr[2:0] Latch MaskShiftReg

6 5 4 3 2 1 0 Hit Sequencing Phi2 pulse that reaches SRAM shift register phi2 phi1 Init hold Address 0 drives DataValid and DataCode to all 0s. Therefore (2^n)-1 sub-regions can be addressed. Addr 0 DataValid 2 channels are hit Logic causes the next SRAM to also receive a write-enable signal. Not a problem: Would be overwritten with valid data or ignored in readout Timestamp 0x008E 0x008F we1 we2 we3 we3

Row 1 [3 hits] Row 2 [0 hits] Row 3 [1 hit] Readout Sequencing phi3 phi1 readInit 1 2 3 readEnables 4 First numbered readEnable is driven from outside to commence readout; all others derive from previous row =(n-1) Note possible combinational delay when passing through empty rows (n=2) Cell being read

Area Estimates 5080um ~16.5u ~25.5u 26 bits ~ 100um 19 registers ~ 50um Mask + sample Mask + sample Mask + sample Select logic SRAM controller SRAM controller Mux Logic + Buffering Local data buffers for global readout Mask: 8.5um per 16 channels Bidir SR: 8.2um per 10 cells

Test Bump Pads Test Structures Pad & Power Ring Control  64x64  64x64 Pixels 10mm  64x64  64x64 Readout 10mm Layout Example 4000um 4000um 200um 200um 1800um 1800um  80 pixels 4000um 36 pixels 36 pixels Readout + I/O buffers

    2mm x 4mm    

Logic Simulation Row Control Logic Verilog Stimulus SRAM Readout

Program Mask Register Mask = 111111000000111111111111111111111111 Mux Addr =101 000 001 101 100 110 Clear & Initialise Logic Hit1 = 000000000000001100000000000000000000 1st Bunch Crossing: 1 hit (Masked hit) 2nd Bunch Crossing: 1 hit Hit2 = 000000010000000000000000011101000000 3rd Bunch Crossing: 2 hit Hit3 = 100001000000000000000000000000010010 Initialise for readout 3rd 3rd 2nd 1st Readout Data = 0101000011111111111100 Readout Data = 1100100101111111111100 Readout Data = 1000111011111111111101 Readout Data = 0010011001111111111110 Readout Addr Hit Pattern Timestamp

2us 36 registers @ approx 18 Mhz 0.5 us 20 registers @ approx 24 Mhz 148ns 148ns Mux address cycles 6 addresses @ 45 Mhz 148ns 50ns 170ns 4 registers @ approx 24 Mhz Program Mask Register Clear & Initialise Logic 1st Bunch Crossing: 1 hit 2nd Bunch Crossing: 1 hit 3rd Bunch Crossing: 2 hit Initialise for readout Readout

Questions • Number of sub-sets of pixels? • 6 or 7 • Number of pixels in a sub-set? • 6 or 7 or 8 Currently Implemented 36 pixels = 1800 um Control logic + SRAM = 200 um Dead Area = 10 % (19 regs)

Question • Assuming a row must be reset after a hit (real or noise)… • This reset is likely to occupy the next bunch crossing, ie lasting 150ns, during which time the N pixels in this row will be ‘blind’ to a subsequent hit (real or noise) • Is this acceptable?

Tera-Pixel APS for CALICE