1 / 9

System Level Timing Analysis

System Level Timing Analysis. Q. Q. D. D. FF2. Required Timing Analyses. B. FF1. G2. G1. A. C. CLK. TCLK=CLK Period. The circuit must be analyzed to show that the set-up (t SU ) and hold (t H ) times of FF2 are met under worst-case conditions. Analysis Assumptions.

lew
Télécharger la présentation

System Level Timing Analysis

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. System Level Timing Analysis

  2. Q Q D D FF2 Required Timing Analyses B FF1 G2 G1 A C CLK TCLK=CLK Period The circuit must be analyzed to show that the set-up (tSU) and hold (tH) times of FF2 are met under worst-case conditions.

  3. Analysis Assumptions • The propagation delay of G1, tPDG1, includes all the delays from CLK to the clock input of FF1: tPDG1 = The connection delay from CLK to G1 input + delay of G1 itself + connection delay from G1 output to FF1 clock input • Similarly for G2 • Similarly, tPDFF1 includes the connection delay from the FF1 output to FF2 input

  4. Set-up Time Analysis tSU@FF2 = TCLK - Slowest Data + Fastest CLK = TCLK - (tPDG1Max + tPDFF1Max) + tPDG2Min tPDDataMax tPDG2Min CLK B C tSU

  5. Hold Time Analysis tH@FF2 = Fastest Data - Slowest CLK = tPDG1Min + tPDFF1Min - tPDG2Max tPDDataMin CLK B C tH tPDG2Max

  6. Hold Time Support Optional delay is matched to the clock distribution delay to make tH = 0 ns.

  7. Clock Skew • If the clock is slower than the data, then the wrong value will be transferred from FF1 to FF2 • tH@FF2 = tPDG1Min + tPDFF1Min - tPDG2Max < 0 If tPDG2Max > tPDG1Min + tPDFF1Min Should latch this Latches this instead CLK tPDDATA B tPDCLK C tH < 0

  8. Using Minimum Delays • In the tSU and tH equations, the minimum delays are questionable • Minimum delays are supplied by some vendors but not all. • If no guaranteed minimum delay value exists, then the correct value to use is 0 ns.

  9. Minimum Delays and Skew • Given that tPDMin=0 should be assumed unless guaranteed otherwise, we have tH@FF2 = tPDG1Min + tPDFF1Min - tPDG2Max < 0 = 0 + 0 – tPDG2Max < 0 which is true for any tPDG2Max > 0.  Circuits should be more carefully examined for skew effects now that parts are getting faster.

More Related