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PLAs Programmable Logic Arrays

PLAs Programmable Logic Arrays. PLAs Objectives. Explain the operation of a PLA Use a PLA to implement a logic network Given a PLA design, determine the logic functions implemented. Programmable Logic Array (PLA). n Input Lines. AND Array. OR Array. k Word Lines. m Outputs Lines.

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PLAs Programmable Logic Arrays

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  1. PLAsProgrammable Logic Arrays ECEn 224

  2. PLAs Objectives • Explain the operation of a PLA • Use a PLA to implement a logic network • Given a PLA design, determine the logic functions implemented ECEn 224

  3. Programmable Logic Array (PLA) n Input Lines . . . AND Array OR Array . . . ... k Word Lines m Outputs Lines ECEn 224

  4. PLA AND-OR Equivalent F1 = AB’+ C F2 = A’C’ + BC F3 = AB’ + A’C’ F4 = A’C’ + BC + AB’C OR Array AND Array Note: Not every minterm is available ECEn 224

  5. PLA Table Generation F1 = AB’+ C F2 = A’C’ + BC F3 = AB’ + A’C’ F4 = A’C’ + BC + AB’C ECEn 224

  6. Internal PLA Structure Inputs Outputs ECEn 224

  7. Internal PLA Structure Inputs The AND plane lines get pulled up to +V Outputs ECEn 224

  8. Internal PLA Structure Inputs 0 The AND plane lines stay at +V unless one of the connected inputs pulls it low. Outputs ECEn 224

  9. Internal PLA Structure Inputs 1 The AND plane lines stay at +V unless one of the connected inputs pulls it low. Outputs ECEn 224

  10. Internal PLA Structure Inputs The OR plane lines get pulled down to Ground Outputs ECEn 224

  11. Internal PLA Structure Inputs The OR plane lines get pulled down to Ground Outputs ECEn 224

  12. Internal PLA Structure Inputs The OR plane lines stay at GND unless one of the AND plane lines pulls it high. Outputs ECEn 224

  13. Internal PLA Structure Inputs The OR plane lines stay at GND unless one of the AND plane lines pulls it high. Outputs ECEn 224

  14. Internal PLA Structure Inputs The OR plane lines stay at GND unless one of the AND plane lines pulls it high. Outputs ECEn 224

  15. Internal PLA Structure Inputs The OR plane lines stay at GND unless one of the AND plane lines pulls it high. Outputs ECEn 224

  16. Another PLA Representation Inputs Outputs ECEn 224

  17. Programmable Logic Array (PLA) • All inputs and inverted inputs available • Limited number of AND functions • This is the biggest difference between a ROM and a PLA • Complete choice of inputs and inverted inputs for each AND function • OR function for each output • Complete choice of AND functions for each OR function (output) ECEn 224

  18. 1 2 3 4 5 6 8 terms 7 2 8 6 terms or AND plane lines PLA Example Implement these equations: X = ABC + B’D’ + AB’D + C’D’ Y = BC + D’ Z = CD + B’D’ + A’BC in this PLA: How can we implement 8 product terms with 6 AND plane lines? ECEn 224

  19. PLA Example Implement these equations: X = ABC + B’D’ + AB’D + C’D’ Y = BC + D’ Z = CD + B’D’ + A’BC ECEn 224

  20. PLA Example Implement these equations: X = ABC + B’D’ + AB’D + C’D’ Y = BC + D’ Z = CD + B’D’ + A’BC ECEn 224

  21. PLA Example Implement these equations: X = ABC + B’D’ + AB’D + C’D’ Y = BC + D’ Z = CD + B’D’ + A’BC ECEn 224

  22. PLA Example Implement these equations: X = ABC + B’D’ + AB’D + C’D’ Y = BC + D’ Z = CD + B’D’ + A’BC ECEn 224

  23. PLA Example C’D’ is in X and Y and looks useful ECEn 224

  24. B’D’ is in all three functions PLA Example C’D’ is in X and Y and looks useful ECEn 224

  25. B’D’ is in all three functions PLA Example C’D’ is in X and Y and looks useful A’BC and ABC cover a lot of minterms ECEn 224

  26. B’D’ is in all three functions PLA Example C’D’ is in X and Y and looks useful A’BC and ABC cover a lot of minterms The only ones left are AB’ and CD ECEn 224

  27. PLA Example X = C’D’ + B’D’ + AB’ + ABC Y = C’D’ + B’D’ + ABC + A’BC Z = B’D’ + CD + A’BC All of the functions are covered using only 6 product terms How is this possible? ECEn 224

  28. PLA Example X = C’D’ + B’D’ + AB’ + ABC Y = C’D’ + B’D’ + ABC + A’BC Z = B’D’ + CD + A’BC ECEn 224

  29. PLA Example X = C’D’ + B’D’ + AB’ + ABC Y = C’D’ + B’D’ + ABC + A’BC Z = B’D’ + CD + A’BC ECEn 224

  30. PLA Example X = C’D’ + B’D’ + AB’ + ABC Y = C’D’ + B’D’ + ABC + A’BC Z = B’D’ + CD + A’BC ECEn 224

  31. PLA Example X = C’D’ + B’D’ + AB’ + ABC Y = C’D’ + B’D’ + ABC + A’BCZ = B’D’ + CD + A’BC ECEn 224

  32. Summary • Explain the operation of a ROM • Use a ROM to implement a logic network • Explain the operation of a PLA • Use a PLA to implement a logic network • Given a PLA design, determine the logic functions implemented ECEn 224

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