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PART II electronics

PART II electronics. S. Di Falco, M. Incagli, F. Pilo, F. Spinella, G. Venanzoni. Electronics: block diagram. EIB. to ECAL crate. R. dynode. D. Q. 1. +. FF. +.  10. comp. -. -. thresh. Each active channel is amplified and compared to a threshold

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PART II electronics

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  1. PART IIelectronics S. Di Falco, M. Incagli, F. Pilo, F. Spinella, G. Venanzoni

  2. Electronics: block diagram EIB to ECAL crate R dynode D Q 1 + FF + 10 comp - - thresh • Each active channel is amplified and compared to a threshold • If the signal is above threshold a flipflop is set to 1 and the information sent to the ECAL crate where the logic is built

  3. Test of analog part • A simple test circuit has been set up that reads two input channels • The input has been generated both with a LED and with a pulse generator VIN FF MAX976 OPA2690 Input Signals amplifier: OPA2690 (2 ch) comparator: MAX976 (2ch) flipflop: SN74LVC2G74

  4. Test of analog part • We have tested power consumption and timing

  5. power consumption • for 2 channels: 10.39mA on +3V 10.05mA on -2V • total power consumption of analog part is: 25.5mW  216ch = 5.52W • 95% of the total power is taken by the OPA 10.39 mA

  6. power consumption – the DAC • In principle 6 DACs (one per active superlayer) are enough, but • each of them must feed 36 comparators  some further electronics • analog signal from ETRG to EIB  long cables • Possible solution: • use a rowwise EIB, instead of the current columnwise scheme (see part III for more details) • put 1 DAC per each EIB and (locally) feed 9 comp. • total number of DACs is 24 • all the analog part is on the EIB and the trigger board has digital components only

  7. power consumption – the DAC • If the horizontal solution is not (mechanically) possible then the DAC must go on the ETRG  to be designed • The choice of the DAC depends upon the communication protocol; an interesting solution is the MAX5380, which has an I2C interface with 4 possible addresses (can reduce number of wires  see later) . Space qualification? • The consumption is very low (250mA), so no problems in using 24 such devices

  8. Time spread • A threshold of 100MeV corresponds to 110mV after 10 amplification • The time Tcomp (from dynode to comparator front) for a signal of height comparable to the threshold is independent from the threshold itself (within reasonable limits) : Tcomp47nsec

  9. Timing • Threshold = 200 mV signal  10 = 200mV anode dynode signal x10 after comparator Dt = 46.0 nsec

  10. Timing • Threshold = 100 mV signal  10 = 100mV anode dynode signal x10 after comparator Dt = 47.5 nsec

  11. Time spread • A threshold of 100MeV corresponds to 110mV after 10 amplification • The time Tcomp (from dynode to comparator front) for a signal of height comparable to the threshold is independent from the threshold itself (within reasonable limits) : Tcomp47nsec • Tcomp31 nsec for a very high signal, due to the OPA slewing rate

  12. Timing • Threshold = 200 mV signal  10 = 2V anode dynode signal x10 after comparator Dt = 31.6 nsec

  13. Time spread • A threshold of 100MeV corresponds to 110mV after 10 amplification • The time Tcomp (from dynode to comparator front) for a signal of height comparable to the threshold is independent from the threshold itself (within reasonable limits) : Tcomp47nsec • Tcomp31 nsec for a very high signal, due to the OPA slewing rate • The maximum time spread is 20 nsec, including transit time spread inside fibers • The cable length can differ for up to 96cm (see later) for different EIBs; small contribution to time spread

  14. Fast Trigger absolute timing 20ns 50ns 50ns TFT = Time Fast Trigger : EIB  50ns EDR (TTL receiver)  20ns ETRG (at least 2 layers)  50ns JLV1 (AND of 2 views)  20ns PMT + CABLES  40ns Total 180ns TTL signal backplane X view 20ns 10ns 5ns 15ns 10ns EIB EDR ETRG JLV1 backplane TTL signal Y view

  15. Level 1 absolute timing • A simple test done with an Altera 20k100-1 (~ same timing of the Actel) with a Verilog logic description shows that the time strictly taken by the parallel logic is of the order of 100 nsec • Even including some pipeline levels the time is well within the 1msec budget • X and Y views are done separately and the JLV1 has to perform the AND of the 2 views

  16. Summary of Signals to JLV1 • Type of signals: LVDS via front panel • List of signals: ECAL-XF 2 out of 3 layers in the X view (fast trigger) ECAL-YF 2 out of 3 layers in the Y view (fast trigger) ECAL-XA Angular cut along X view ECAL-YA Angular cut along Y view • Trigger conditions: ECAL-FTECAL-XF & ECAL-YF (fast trigger) ECAL-L1gamECAL-XA & ECAL-YA & ECAL-FT ECAL-L1eleAECAL-XF & ECAL-YF (veto of ACC) ECAL-L1eleSECAL-L1gam (e standalone)

  17. Summary of part II • Results from (simple) test : • power consumption of analog part : 5.5 Watts • max time spread at fast trigger level : 20nsec • TFT = 180nsec • TL1 < 1msec • Preferred solution from the DAC point of view: • horizontal EIBs with 9 PMTs each • 24 DACs (low power consumption) • All analog components on EIB • Redundancy : • at the EIB level depends upon component selection: OPA 960 red. 1, OPA2960 red. 1/2, OPA 3960 red. 1/3 • at the ETRG level the standard factor 2 • Interface with level 1 : • 2 LVDS cables from each ETRG

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