32-BIT ADDER FOR LOW VOLTAGE OPERATION WITH LEVEL CONVERTERS

1. 32-BIT ADDER FOR LOW VOLTAGE OPERATION WITH LEVEL CONVERTERS PRIYADHARSHINI S

2. OBJECTIVES • To reduce power consumption in a 32-bit adder circuit by reducing the voltage of operation • To study the effect of voltage reduction on the delay of the circuit • To identify an optimal voltage of operation at which the power-delay product is low • To design a level converter to make the circuit compatible with other circuits

3. TOOLS USED • ModelSim: To verify the functionality of the circuit • Leonardo Spectrum: To synthesize the verilog gate level netlist • MATLAB: To synthesize the netlist compatible with PowerSim • Design Architect: To obtain the transistor level design of gates • LTSpice: To evaluate the delays of individual gates • PowerSim: To assess the performance of the circuit at different voltages

4. ModelSim (functional verification) Outputs PowerSim Tutorial – Manish Kulkarni http://www.eng.auburn.edu/~vagrawal/COURSE/E6270_Spr09/course.html

5. LOW VOLTAGE OPERATION • I = K (VGS - VT )2 / 2 • R α 1/I • Resistance increases as voltage reduces • Time constant = RC • Delay increases as voltage decreases 0V

6. LOW VOLTAGE OPERATION • Dynamic Power = αCV2 • Dynamic Power reduces with voltage reduction Gonzalez, R., Gordon, B.M., Horowitz, M.A., Supply and Threshold Voltage Scaling for Low Power CMOS, IEEE Journal of Solid-State Circuits, Aug 1997, Volume 32, Issue 8 http://www.eng.auburn.edu/~vagrawal/COURSE/E6270_Spr09/course.html - Lecture 4 Power Dissipation of CMOS circuits

7. POWER CALCULATION • Dynamic power α V2f • Power = kV2/T • At a voltage of 1.1 V (normal operation) • Dynamic power = 232.72 µW • T = 650 ps • => k = 0.125 p mho • Power = 0.125 V2/T pW

8. DELAY CALCULATION • Delay = K V/ (V – Vth)α • At 1.1 V, Delay = 625 ps • At 1.0 V, Delay= 640 ps • K = 420 ps • α = 0.73 • Delay = 420 V/ (V – Vth)0.73 Gonzalez, R., Gordon, B.M., Horowitz, M.A., Supply and Threshold Voltage Scaling for Low Power CMOS, IEEE Journal of Solid-State Circuits, Aug 1997, Volume 32, Issue 8

9. DYNAMIC POWER in adder circuit(µW)

10. DELAY in adder circuit (ps)

11. CIRCUIT SETUP VDD_L VDD_H VDD_L VDD_L VDD_H HIGH TO LOW CONVERTER ADDER CIRCUIT LOW TO HIGH CONVERTER

12. HIGH TO LOW converter – not required 0.5V 1.1 V 0.5V 1.1 V Will not turn off PMOS Can turn off PMOS and can turn on NMOS VGS< Vth for PMOS to be turned on Vthp= -0.43 V

13. LEVEL CONVERTER

14. LEVEL CONVERTER OPERATION Level Converter for CMOS 3V to from 5V United States Patent [19] Masaki et al. Patent Number: 5,680,064 Date of Patent: Oct. 21, 1997

15. RESULTS Number of gates in adder =128 Approximate increase in area = 25.78%

17. CONCLUSION • The adder circuit can be operated at 0.5V in order to minimize power • Parameters other than power-delay product should be considered to decide on the operating voltage

18. FUTURE WORK • Evaluating performance of circuit with a few chains of gates operating at low voltages • Lowering power by introducing low-threshold transistors in non-critical paths

19. REFERENCES • Gonzalez, R., Gordon, B.M., Horowitz, M.A., Supply and Threshold Voltage Scaling for Low Power CMOS, IEEE Journal of Solid-State Circuits, Aug 1997, Volume 32, Issue 8 • Anantha P. Chandrakasan, Samuel Sheng, Robert W. Brodersen, Low-Power CMOS Digital Design, IEEE Journal of Solid-State Circuits, Volume 27, No.4, April 1992 • Masaki et al., Level Converter for CMOS 3V to from 5V, United States Patent [19] Patent Number: 5,680,064 Date of Patent: Oct. 21, 1997 • Kiat-SengYeo, Kaushik Roy, Low-Voltage, Low-Power VLSI Subsystems, McGraw Hill • Class lectures

20. THANK YOU