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Viterbi Decoder Project

Viterbi Decoder Project. Alon weinberg, Dan Elran Supervisors: Emilia Burlak, Sara Galan. Appendix- cage operation.

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Viterbi Decoder Project

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  1. Viterbi Decoder Project Alon weinberg, Dan Elran Supervisors: Emilia Burlak, Sara Galan

  2. Appendix- cage operation This is the appendix to the Viterbi Decoder project, in which we learn how to operate the cage (donated by Qualcomm Israel) and write a small module that demonstrates the cage operation- shows how the FPGA works, how the DSP works and how they both work together in harmony.

  3. The Cage

  4. The board (FMC)

  5. The board (FMC)

  6. Board bus rates • DSP works at 160 MHz • BUT Arbiter works at 40 MHz (Bottleneck) • Periferial BUS (PCI) • Local Bus • PLX and DSP can master both buses • Asynched I/O RAMs connected to FPGAs

  7. PES PES is the software running on the VXWorks RT OS on the cage, written by Qualcomm Israel. It is the Cage Driver, and has service functions like reading and writing memory addresses on the FPGA/DSP.

  8. Code Uploading • Hex files • FTP to cage • /FIRMWARE/FMC/ for FPGA code (same for both FPGAs) • /DSP/FMC/ for DSP code • Reboot

  9. Connecting • CRT (or similar?) • Telnet (IP address) or serial cable (if serial- 9600 Baud rate, no flow control)

  10. Connecting (cont.)

  11. Memory access (PES) • Mww(slot number, address, value) • Mrw (slot number, address) • Add 2 to the PES slot number • Base addresses- in HSID

  12. Memory access (DSP C code) • CONTENTS_OF( address) • Base addresses- in the C header files

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