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Viterbi Decoder VLSI Design Project Spring 2002

Viterbi Decoder VLSI Design Project Spring 2002. Dan Breen Keith Grimes Damian Nowak David Rust Advisor: Prof. Goeckel. Definition of Feasibility. Capable of being done or carried out. Reasonable, Likely. Digital Communication System. “Few Bits”. “More Bits”. Source Encoder.

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Viterbi Decoder VLSI Design Project Spring 2002

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  1. Viterbi DecoderVLSI Design ProjectSpring 2002 Dan Breen Keith Grimes Damian Nowak David Rust Advisor: Prof. Goeckel

  2. Definition of Feasibility • Capable of being done or carried out. • Reasonable, Likely

  3. Digital Communication System “Few Bits” “More Bits” Source Encoder Channel Encoder Modulator Source Redundancy to Reduce Probability of Error Effective Channel with Probability 0.1 – 0.01 of flipping a bit A/D Conversion Compression Channel Source Decoder Channel Decoder Demodulator User Reconstruct Original Signal Guesses the “More Bits” Viterbi Decoder - with Probability of Error of about 0.00001

  4. Parameters • Rate = 1/2 • Constraint Length (K) = 3

  5. Channel Encoder 0 1 1 + 1-Bit Register 1-Bit Register Input 0 1 0 + 0 1 0 Output = 00 11 10 Rate = 1/2 K = 3

  6. Trellis Diagram – Heart of the Viterbi Decoder Enumerates all possible encoded sequences (basically a FSM transitioning with time)

  7. Viterbi Decoder Block Diagram Hamming Distance Compute Metric Input Compare Select Path Select Path Memory Output

  8. Hamming Distance • Bit-wise XOR comparison of received channel symbol pair and possible channel symbol pairs. • I.e. the hamming distance between 01 and 11 would be 1, and the hamming distance between 01 and 10 would be 2.

  9. Hamming Distance Distance with Hamming Distance Module 00 2 01 2 Input 10 2 2 11 2

  10. Compute Metric • Add the previous accumulated error metric to the current calculated hamming distance.

  11. Compute Metric From Compare Select 3 3 3 3 Compute Metric Module 2 4 . . . From Hamming Distance 2 8 Error Metrics 2 2 4

  12. Compare Select • Determines the smallest accumulated error metric entering each state. • Reduces magnitude of accumulated error metric to prevent register overflow.

  13. Compare Select To Compute Metric 3 3 3 3 Compare Select Module 4 4 From Compute Metric {0..7} . . . 4 To Path Memory 4 4 4

  14. Path Memory • Stores the 4 possible paths through the trellis with their associated accumulated error metrics. • Retains at least 5 * (K-1) previous trellis stages.

  15. Path Memory Path Memory Module 4 4 From Compare Select {0..3} . . . . . . To Path Select {0..3} 4 4

  16. Path Select • Selects path with the lowest accumulated error metric and performs traceback and decoding.

  17. Path Select Path Select Module 4 From Path Memory {0..3} . . . 1 Decoded Output 4

  18. Conclusion • Yes…It is Feasible. • Next…complete modules and perform testing and verification of Viterbi decoder.

  19. References • Communication Systems Engineering,1st edition (1994). John G. Proakis and Masoud Salehi. Prentice Hall. • “Lecture #14: Convolutional Codes” (Fall 1992). Kim Winick. • “A Tutorial on Convolutional Coding with Viterbi Decoder” (Nov 2001). Chip Fleming. • Advisor Lecture Notes (Feb 2002). Dennis Goeckel. • http://www.m-w.com/cgi-bin/dictionary Project Web Page http://home.attbi.com/~dlrust/Viterbi.html

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