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Digital Testing: Built-in Self-test

Digital Testing: Built-in Self-test

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Digital Testing: Built-in Self-test

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  1. Digital Testing: Built-in Self-test Based on text by S. Mourad "Priciples of Electronic Systems"

  2. Outline • BIST and embedded testing • Why BIST • Primitive polynomials • LFSR • Response compression • BILBO

  3. Define Built-In Self-Test • Implement the function of automatic test equipment (ATE) on circuit under test (CUT). • Hardware added to CUT: • Pattern generation (PG) • Response analysis (RA) • Test controller CK PG Stored Test Patterns Pin Electronics CUT Test control logic CUT Test control HW/SW BIST Enable RA Stored responses Comparator hardware Go/No-go signature ATE

  4. Built-in self-test Disadvantage of LSSD & other scan techniques: 1. Test generation necessary for combinational part 2. Long test time since test have to be shifted in & out 3. Only stuck-at faults are tested - not good for VLSI

  5. Built-in self test Test generation is NP complete. This prompted a search for built-in structures * Built-in self test BIST is an alternative to automatic test vector generation * Test generation & verification done by circuits built into the chip * Pseudo-random test vector generation is accomplished by using shift registers

  6. Built-in self-test in VLSI • Test patterns generated on chip • responses to test evaluated on chip • external operations only to initialize test & clock • go no go results • additional pins & silicon area minimized

  7. Built-in self test types • operation • (concurrent or not) • test design • (exhaustive or not) • test vector generation • (deterministic or pseudorandom) • data compression • (full or compresses test vectors)

  8. A general built-in self test approach

  9. Built-in self test * Deterministic testing identifies test vectors to detect specific faults * Pseudorandom testing detects # of faults by any test vector * Fault coverage increases rapidly at the beginning and slows down towards the end * The response data is compressed using a signature analysis * Linear feedback shift registers (LFSR) used to generate test vectors and compress responses

  10. Pseudorandom Integers Xk = Xk-1 + 3 (modulo 8) Xk = Xk-1 + 2 (modulo 8) 0 0 7 1 7 1 Start Start 6 2 6 2 +3 +2 5 3 5 3 4 4 Sequence: 2, 5, 0, 3, 6, 1, 4, 7, 2 . . . Sequence: 2, 4, 6, 0, 2 . . . Maximum length sequence: 3 and 8 are relative primes.

  11. Pseudo-Random Pattern Generation • Standard Linear Feedback Shift Register (LFSR) • Produces patterns algorithmically – repeatable • Has most of desirable random # properties • May not cover all2n input combinations • Long sequences needed for good fault coverage either hi = 0, i.e., XOR is deleted or hi = Xi Initial state (seed): X0, X1, . . . , Xn-1 must not be 0, 0, . . . , 0

  12. Y0 Q D Q Q D D Clk Q Q Q (a) Y Y Y 1 2 3 Y 0 Q Q D Q D D Clk (b) Q Q Q Y Y Y 1 2 3 Y 0 Q Q Q D D D Clk Q Q Q (c) Y Y Y 1 2 3 Pseudo-Random Pattern Generator Various LFSR configurations

  13. (a) (b) (c) Clk Y0 Y1Y2Y3 ClkY0 Y1Y2Y3 ClkY0 Y1Y2Y3 1 001 1 001 1 001 1 1 100 1 0 100 1 1 100 2 1 110 2 0 010 2 0 110 3 0 111 3 1 001 3 0 011 4 1 011 4 1 001 5 0 101 6 0 010 7 1 001 Initial state Y0 Q D Q Q D D Clk Q Q Q (a) Y Y Y 1 2 3 Y 0 Q Q D Q D D Clk Repeated states Q Q Q (c) Y Y Y 1 2 3 Pseudo-random Patterns

  14. Forcing all possible states in LFSR Modified LFSR • Clk Y0 Y1Y2Y3 Y1’Y2’ • 0 001 1 • 1 1 000 1 • 2 1 100 0 • 3 1 110 0 • 0 111 0 • 5 1 011 0 • 6 0 101 0 • 0 010 0 • 0 001 1 Produces pseudorandom sequence of length 8 Initial state

  15. Standard LFSR XOR operations performed outside of the shift register

  16. Modular LFSR XOR operations performed inside the shift register

  17. Linear feedback shift registers Two basic configurations : - internal XOR (IE) - external XOR (EE) Feedback connections based on coefficients of a characteristic polynomial : P(X) = C0 + C1X + C2X2 +…+ CnXn An LFSR with n-flip flops can assume (2n-1) states with depend upon : initial state, input, and feedback

  18. EXTERNAL CONNECTIONS (STANDARD) 2 3 4 1 X X X X INTERNAL CONNECTIONS (MODULAR) 4 3 2 X X X X 1 3 4 P(X) = 1+ X + X Characteristic Polynomial Linear feedback shift registers

  19. Y 0 Q D D Q D Q Y0 Q D Q Q D D Clk Q Q Q Clk Y Y Y Q Q Q (a) 1 2 3 Y Y Y 1 2 3 LFSR Equivalence P(X)=1+X+X3

  20. Test generation in BIST LFSR generally works without input - so only the initial state & interconnections decide the next state A generator which generates exactly (2n-1) different states is called a maximal-length generator All polynomials are either primitive (irreducible) or nonprimitive

  21. Test generation in BIST A primitive polynomial generates a max length sequence of test vectors. The number of primitive polynomials of order n grows rapidly with n p - any prime number which divides (2n-1)

  22. Modulo 2 Operations a b a  b a+b a+b a-b a - b sum carry difference borrow 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 0 1 1 0 1 0 • 1 0 0 1 0 0 Define time translation operation as X k = X (t-k)

  23. Math Foundation of LFSR Yj can be represented as: Yj(t) = Yj-1(t - 1) for j  0 We can express Yj in terms of Y0 as: Yj (t) =Y0(t - j) Denote the translation operator as X k, where k represents the time translation units, then Yj (t) =Y0(t)X j On the other hand in LFSR Where the summation is equivalent to an XOR operation. Then we get

  24. Math of LFSR Generators From linearity we have and We can then write this expression as Y0 (t) PN (X) = 0 For non-trivial solutions, Y0(t)  0, then we must have PN (X) = 0. Where, PN (X) is called the characteristic polynomial of the LFSR.

  25. Primitive Polynomials • Examples of primitive polynomials with minimum number of terms • N Polynomials • 1,2,3,4,6,7,15,22 1 + X + Xn • 3,5,11, 21, 29 1 + X2 + Xn • 10,17,20,25,28,31 1 + X3 + Xn • 9 1 + X4 + Xn • 23 1 + X5 + Xn • 18 1 + X7 + Xn • 8 1 + X2 + X3 + X4 + Xn • 12 1 + X + X3 + X4 + Xn • 13 1 + X + X4 + X6 + Xn • 14, 16 1 + X + X3 + X4 + Xn

  26. Test generation in BIST For instance for n=8 a minimum polynomial is Example : Let us follow test generation using a primitive polynomial

  27. Reciprocal Polynomials The reciprocal polynomial of P(X) is defined by: so PR(X) = XN + Cj XN-j for 1  j N Thus every coefficient Cjin P(X) is replaced by CN-j in PR(X) For example, the reciprocal of polynomial P(X) = 1+ X+ X3 is PR(X) = 1+ X2 + X3

  28. Operations on Polynomials • Polynomial multiplication • x4 + x3 + + 1 • . x + 1 . • x4 + x3 + + 1 • x5 + x4+ + x . • x5 + + x3 + x + 1 since x4 + x4 = 0. • Division is of particular interest when LFSRs are used for response compaction. • x2 + x + 1 . • x2 + 1 ) x4 + x3 + + 1 • x4 + + x2 . • x3 + x2 + + 1 • x3 + + x . • x2 + x + 1 • x2 + + 1 • x • the reminder R(x)=x

  29. Operations on Polynomials • Reminder of the division of the input sequence polynomial by the • LFSR polynomial gives the signature for the compacted response • Q(X) X4 + X3 + 1 1 1 0 0 1 • X3 + X2 + 1 |X7 + X5 + X4 + +1 1 1 0 1 | 1 0 1 1 0 0 0 1 • X7 + X6 + X41 1 0 1 • X6 + X5 +1 1 1 0 0 0 0 1 • X6 + X5 + +X31 1 0 1 • X3 + +1 1 0 0 1 • X3 + X2 + 11 1 0 1 • R (X) X2 0 1 0 0 signature Polynomial for the input data

  30. Properties of Polynomials • An irreducible polynomial is that polynomial which cannot be factored and it is divisible by only itself and 1. • An irreducible polynomial of degree n is characterized by : • An odd number of terms including the 1 term • Divisibility into1 + xk, where k = 2n - 1. • Any polynomial with all even exponents can be factored and hence is reducible • An irreducible polynomial is primitive if the smallest positive integer k that allows the polynomial to divide evenly into 1 + xk occurs for k = 2n - 1, where n is the degree of the polynomial.

  31. Properties of Polynomials • All polynomials of degree 3 are: • x3 + 1= 0 • x3 + x2 + 1 = 0 Primitive • x3 + x + 1 = 0 Primitive • x3 + x2 + x + 1= 0 • But, x3 + 1= (x + 1)( x2 + x + 1) • x3 + x2 + x + 1 = (x + 1)( x2 + 1) • There are several primitive polynomial of degree N. • We are interested in those with fewer terms since they need less XOR gates in the LFSR. • Among primitive polynomial of degree 16 are x16 + x5 + x3 + x2 + 1 and x16 + x4 + x3 + x + 1.

  32. Check for Primitive Polynomial • Consider a 3-rd order primitive polynomial x3 + x + 1 = 0 • If this polynomial is primitive it must divide evenly into 1 + x 7 (7 = 2 3 – 1) where 3 is the degree of the polynomial. We can check that 1 + x 7= (x 3+ x + 1)(x 4 + x 2 + x + 1)

  33. Test data compression • To verify response of a tested circuit use • test data compression • Ones count compression • ex 10011010 => 0(x)=4 • Transition count compression • ex 10011010 => c(x) =5 • Parity check compression • ex 10011010 => p(x) =0 • Syndrome testing (normalized # of 1’s ) • ex 10011010+> s(x) =4/8 • Compression using Walsh spectra • Cyclic code compression (LFSR)

  34. Parity Compression Computes parity

  35. Ones Count If we have a test of length L and the fault-free count is m, then the possibility of aliasing is [C (L, m) - 1] patterns out of total number of possible strings of length L, (2L - 1).

  36. One Count example For m = 5 and L = 8, aliasing probability will be Pa (m) =( C(8,5)-1 ) / (2^8-1) =55 /255  0.2. Not a very reliable method

  37. Transition Count Computes transitions

  38. Signature Analysis Uses LFSR to obtain a signature

  39. LFSR as Response Analyzer • Use cyclic redundancy check code (CRCC) generator (LFSR) for response compacter • Treat data bits from circuit POs to be compacted as a decreasing order coefficient polynomial • CRCC divides the PO polynomial by its characteristic polynomial • Leaves remainder of division in LFSR • Must initialize LFSR to seed value (usually 0) before testing • After testing – compare signature in LFSR to precomputed signature of fault-free circuit

  40. Signature Analysis • LFSR seed is “00000”

  41. Signature by Logic Simulation X0 0 1 0 0 0 1 1 1 1 Input bits Initial State 1 0 0 0 1 0 1 0 X1 0 0 1 0 0 0 0 1 0 X2 0 0 0 1 0 0 0 0 1 X3 0 0 0 0 1 0 1 0 1 X4 0 0 0 0 0 1 0 1 0 Signature

  42. X2 X7 X7 + 1 + X5 X5 X5 + X3 + X3 + X3 X3 + X + X + X X5 + X3 + X + 1 Char. polynomial + X2 + X2 + X2 + 1 + 1 remainder Signature: X0X1X2X3X4 = 1 0 1 1 0 Signature by Polynomial Division Input bit stream: 0 1 0 1 0 0 0 1 0 ∙ X0 + 1 ∙ X1 + 0 ∙ X2 + 1 ∙ X3 + 0 ∙ X4 + 0 ∙ X5 + 0 ∙ X6 + 1 ∙ X7 Polynomial division equivalence of datacompression

  43. Test generation based on a nonprimitive polynomial x4 + x2 +1 generates only 6 out of possible 15 states

  44. Multiple-Input Signature Register (MISR) • Problem with ordinary LFSR response compacter: • Too much hardware if one of these is put on each primary output (PO) • Solution: MISR – compacts all outputs into one LFSR • Works because LFSR is linear – obeys superposition principle • Superimpose all responses in one LFSR – final remainder is XOR sum of remainders of polynomial divisions of each PO by the characteristic polynomial

  45. X0 (t + 1) X1 (t + 1) X2 (t + 1) 0 0 1 1 1 0 X0 (t) X1 (t) X2(t) d0 (t) d1 (t) d2(t) 0 1 0 = + Modular MISR Example

  46. SSA M 1 M 3 4 1 2 2 M 3 M 4 BELLMAC M 1 M 2 LSFR M 3 M 4 PSA M M M M 2 3 4 1 2 3 4 1 2 3 M(X)= M + X M + X M + X M 1 2 3 4 Space Compaction – parallel outputs

  47. Test data compression BIST To reduce the number of response data a compression Based on LFSR (signature analysis) is used. Probability that 2 sequences which differ by 1 bit only will have the same signature is zero Data entering LFSR serially produces a reminder of the division of the data stream polynomial by the polynomial used for LFSR design

  48. A faulty data stream will yield the same signature (reminder of polynomial division) as a fault-free data when they have the same reminder The likelihood of this is in the range of where n is the number of the compressor bits The same effect can be obtained on multi-input shift registers with faster processing speed & smallerchip area. Fault-free signature 2n-1 faulty signatures Test data compression BIST

  49. Test data compression BIST • As in the single-input case the probability of • detecting uniformly distributed fault in the output • stream is (1 - 2-n ) • Probability of not detecting error after • checking its signature is greater than 2-n - the • probability of not catching the signature error. • Example 1: n = 4, Aliasing probability = 6.25% • Example 2: n = 8, Aliasing probability = 0.39% • Example 3: n = 16, Aliasing probability = 0.0015%

  50. LFSR Design Guidelines In using LFSR for data compression: • Chose r large enough to reduce 2-r • Repeat test using different feedback connections • Repeat test with different test vector • Compress serial output of MISR into LFSR to capture errors