Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation

1. Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation Yuanlin Lu Intel Corporation, Folsom, CA 95630 Vishwani D. Agrawal Department of ECE, Auburn University, Auburn, AL 36849 VLSI Design Conference

2. Outline • Motivation • Problem Statement • Background • Proposed Technique • Statistical reduction of leakage and glitch power under process variation • Results • Conclusion VLSI Design Conference

3. Motivation • Leakage power has become a dominant contributor to the total power consumption • 65nm, leakage is ~ 50% of total power consumption • Glitches consume 20%-70% of dynamic power • Variation of process parameters increases with technology scaling • both average and standard deviation of leakage power increase • Glitch elimination technique of path balancing becomes ineffective • Power yield and timing yield are degraded VLSI Design Conference

4. One Example: Process Variation Effect on Leakage and Performance • [Ref] S. Borkar, et. al., DAC 2003. • 0.18um CMOS process • 20X leakage variation • 30% frequency variation • high frequency but too leaky chips must be discarded • low leakage chips with too low frequency must also be discarded too leaky too slow VLSI Design Conference

5. Comparison of Dynamic and Leakage Power Variation of Un-Optimized C432 (1,000 Samples) Nominal Normalized Dynamic Power Normalized Leakage Power VLSI Design Conference

6. Process Variation and Dynamic Power • Dynamic power is normally much less sensitive to the process variation due to its approximately linear relation to process parameters. • Deterministic path balancing becomes ineffective under process variation because the perfect hazard filtering conditions can easily be corrupted with a very slight variation in process parameters. Nominal C432 unoptimized for glitches C432 optimized by path balancing VLSI Design Conference

7. Previous Work and Problem Statement • Previous Work: Mixed integer linear program (MILP) for optimum Dual-Vth and delay buffer assignment for • Minimum leakage • Glitch elimination • Overall delay specification • Lu and Agrawal, “CMOS Leakage and Glitch Minimization for Power-Performance Tradeoff,” JOLPE, vol. 2, no. 3, pp. 1-10, December 2006. • Lu and Agrawal, “Statistical Leakage and Timing Optimization for Submicron Process Variation,” Proc. 20th Int. Conf. VLSI Design, Jan. 2007, pp. 439-444. • Problem Statement: Minimize leakage and glitch power considering process variation. VLSI Design Conference

8. 1 2 2 1 2 2 Techniques to Eliminate Glitches ? path delay difference < gate inertial delay [1] • Hazard Filtering (Gate/Transistor Sizing) • Increase gate inertial delay • Sizing gate to change gate delay • Path Balancing • Decrease path delay difference • Insert delay elements on the shorter delay signal path →3 1.5 →0.5 [1] V. D. Agrawal, International Conference on VLSI Design, 1997 VLSI Design Conference

9. Glitch Elimination • For every gate i: • Without process variation: | Ti – ti | ≤ Di • With process variation: Prob{ | Ti – ti | ≤ Di } ≥ η Signal arrival time window [ ti, Ti] Inertial delay Di Di = Xi Di(low Vth) + (1 – Xi) Di(high Vth), Xi = [0,1] Leakage(i) = Xi Leajage(low Vth) + (1 – Xi) Leakage (high Vth) VLSI Design Conference

10. A Mixed Integer Linear Programfor Leakage and Glitch Power Reduction Objective function (linear approximation): Minimize {C1·Total leakage + C2·Total glitch suppressing delays} VLSI Design Conference

11. Minimize" i Î gate number Subject to" k Î PO Minimize" i Î gate number Subject to" k Î PO MILP Formulation (Deterministic vs. Statistical) Deterministic Approach The delay and subthreshold current of every gate are assumed to be fixed and without any effect of the process variation. Basic MILP – Minimize total leakage while keeping the circuit performance unchanged. Statistical Approach Treat delay and timing intervals as random variables with normal distributions; leakage as random variable with lognormal distribution Basic MILP – Minimize total nominal leakage while keeping a certain timing yield (η). VLSI Design Conference

12. Delay Distribution without Considering Process Variation Circuits unoptimized for glitch Circuits optimized for glitch by path balancing VLSI Design Conference

13. Delay Distribution under Process Variation Circuits unoptimized for glitch Circuits optimized for glitch by path balancing Glitch power of unoptimized circuits is not sensitive to process variation; Glitch power of circuits optimized by path balancing is sensitive to process variation. VLSI Design Conference

14. Technique of Enhancing the Resistance of Glitch Power to Process Variations • Leave a relaxed margin for process variation resistance in advance VLSI Design Conference

15. Results for C432 Monte Carlo Simulation (15% local process variation) • C432 optimized by the statistical MILP with greater emphasis on glitch power to process variation (blue) • C432 optimized by the deterministic MILP (Purple) Dynamic Power (logic simulation) Subthreshold Leakage (Spice simulation) VLSI Design Conference

16. Results of MILP:Leakage Power Distribution of Optimized Dual-Vth C7552 Mean and Standard Deviation of leakage power are reduced by the statistical method. VLSI Design Conference

17. Conclusion • Circuits optimized of glitch suppression can be seriously degraded by process variation. • Overdesign (3σ variation) may reduce sensitivity to process variation. • Statistical design (specified yields) can give improved tradeoffs between leakage power, glitch power and timing. VLSI Design Conference

18. gate delay + LVT design 2 2 3 7ns = + 2 3 3.2 8.2ns = + + dual-Vth design 1 2 3 FF FF 8ns Future Work Iterative MILP for dual-Vth design • Timing violations were found • The interdependency of delays of gates was neglected for simplicity in our MILP formulation. • If any timing violation is found, the new delays for all LVT cells are extracted from the current dual-Vth design and the MILP formulation is updated correspondingly. A different optimal solution is then given by the CPLEX solver with fewer timing violations. We continue iterations until all timing violations are eliminated. VLSI Design Conference

19. Thank You All !Questions? VLSI Design Conference