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A Pedagogically Targeted Logic Simulation Tool

David A. Poplawski Department of Computer Science Michigan Technological University Houghton, MI 49931 pop@mtu.edu. A Pedagogically Targeted Logic Simulation Tool. Eric Simonton Benny Evans, Eric Dalquist, Jonathan Evan Zack Kurmas (GVSU) MTU and GVSU Comp. Org. students.

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A Pedagogically Targeted Logic Simulation Tool

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  1. David A. Poplawski Department of Computer Science Michigan Technological University Houghton, MI 49931 pop@mtu.edu A Pedagogically TargetedLogic Simulation Tool Workshop on Computer Architecture Education

  2. Eric Simonton Benny Evans, Eric Dalquist, Jonathan Evan Zack Kurmas (GVSU) MTU and GVSU Comp. Org. students Acknowledgements Workshop on Computer Architecture Education

  3. Workshop on Computer Architecture Education Design Goals • Computer Organization/Architecture Courses • Student Circuit Design Projects • In-Class Concept Demonstrations • Powerful GUI • Batch (non-GUI) Grading • Easy To Use • Comprehensive • Be The Best Available

  4. Workshop on Computer Architecture Education Student Needs • Simple Graphical User Interface • Shallow Learning Curve • Tutorials and On-Line Help • Early Error Detection • Support for Circuit Debugging

  5. Workshop on Computer Architecture Education Instructor Needs • Shallow Learning Curve • Classroom Demonstrations • Fast Circuit Construction and Modification • Intuitive Circuit Operation Observation • Testing/Grading Student Projects • Batch (non-GUI) Execution (scripts) • Externally Forced Circuit Properties • Externally Provided Inputs (initial and time varying) • Circuit, Signal Trace, and Output Printing

  6. Workshop on Computer Architecture Education Time for a Test Drive ...

  7. Workshop on Computer Architecture Education Batch Operation • jls -Pmylaser circuit.jls • prints the circuit to the specified printer • jls -Rmylaser circuit.jls • runs the circuit, prints signal trace • jls -b circuit.jls • Runs the circuit, prints final values of “watched” elements

  8. Simulation Stopped at 262030 Register PC: 0x20 (32 unsigned, 32 signed) Changed locations in memory Memory.Memory 0xa: 0x0 (0 unsigned, 0 signed) -> 0x37 (55 unsigned, 55 signed) Watched Element Output Workshop on Computer Architecture Education

  9. Workshop on Computer Architecture Education Batch Input Signal Generation • Specify a signal generator file (command line) • Runs circuit with specified input sequence • Use with trace-print option to get hard copy

  10. Workshop on Computer Architecture Education Startup Parameter File • Used to Force Circuit Properties • Set propagation delays by element type • Set specific element propagation delay (by name) • Remove all watches and/or probes • Make specific elements watched (by name) • Give registers initial values • Specify memory element initialization-file-name • Element Locking

  11. Workshop on Computer Architecture Education Availability • Applet Version: • www.cs.mtu.edu/~pop, then click on the JLS icon • No file input/save, no printing, etc. • Full JLS • Two Java “jar” files, easy to install • Send email to pop@mtu.edu for a copy and to be put on the update mailing list • Circuit Library • User contributed, password protected

  12. Workshop on Computer Architecture Education What's Next? • Minor convenience enhancements • Orientation flexibility • More keyboard shortcuts • More efficient overlap detection • Subcircuit linking (versus inclusion) • Automated grading system • Zack Kurmas, Grand Valley State University • Export to VHDL and/or Verilog • Extensibility (plugins)

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