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CMOS Technology

CMOS Technology. Flow varies with process types & company N-Well CMOS Twin-Well CMOS Start with substrate selection Type: n or p Doping level, → resistivity Orientation, 100, or 101, etc Other parameters. A Twin-Well Process Flow. Initial cleaning Growth of SiO 2 layer

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CMOS Technology

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  1. CMOS Technology • Flow varies with process types & company • N-Well CMOS • Twin-Well CMOS • Start with substrate selection • Type: n or p • Doping level, →resistivity • Orientation, 100, or 101, etc • Other parameters

  2. A Twin-Well Process Flow • Initial cleaning • Growth of SiO2 layer • Deposition of Si3N4 layer • Spun photoresist layer

  3. Apply mask 1 Photo process Dry etch of unprotected area

  4. Strip photoresist Grow field oxide

  5. Etch out Si3N4, spin photoresist Apply mask 2, photo process, etch Boron implant, form P well for NMOS

  6. Etch out photoresist, spin new layer Apply mask 3, photo process, etch N-type implant, form N well for PMOS

  7. Etch out photoresist High temp drive-in to complete wells

  8. Spin photoresist, apply mask 4 Photo process, etch Boron implant to adjust N-channel VT

  9. Spin new photoresist, apply mask 5 Photo process, etch Arsenic implant to adjust P-channel VT

  10. Remove photoresist, and thin oxide Grow gate oxide with precise thickness

  11. Deposit polysilicon layer Phosphorous implant to heavily dope the poly

  12. Spin photoresist Apply mask 6, photo process Plasma etch to remove poly

  13. Remove old and spin new photoresist Apply mask 7, photo process N- -type implant

  14. Remove old and spin new photoresist Apply mask 8, photo process P- -type implant

  15. Remove photoresist Deposit a conformal layer of SiO2

  16. Anisotropically etch SiO2 layer Form sidewall spacers by poly

  17. Grow thin “screen” oxide Spin photo resist, apply mask 9 Arsenic implant to form drain, source

  18. Photoresist, mask 10 Boron implant (P+) for PMOS’ S & D

  19. High-temp drive-in to activate implanted dopants and diffuse junction to their final depth

  20. Unmasked etch to remove oxide from drain, source, and gate tops

  21. Deposit titanium layer by sputtering

  22. Titanium reacts in N2 ambient Form TiSi2 when in contact with Si Elsewhere form TiN

  23. Spin photoresist Mask 11 to protect local interconnects Etch remaining TiN

  24. Remove photoresist Deposit conforming SiO2 layer

  25. CMP (chemical-mechanical polish) Polish SiO2 and planarize wafer surface

  26. Spin photoresist Mask 12 for contact holes Etch SiO2 to expose poly or TiN

  27. Deposit a thin TiN barrier/adhesion Deposit a W layer

  28. CMP

  29. Deposit Al, spin photoresist Mask 13 Plasma etch

  30. Repeat several step for metal 2 with mask 14 and 15 Passivation layer, mask 16 for bonding pads

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