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CMOS Transistors

CMOS Transistors. Outline. Qualitative Description of CMOS Transistor g m /I D Design Biasing a transistor Using g m /I D Approach Design Using Cadence. A Crude Metal Oxide Semiconductor (MOS) Device . V2 causes movement of negative charges, thus current. V1 can control the

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CMOS Transistors

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  1. CMOS Transistors

  2. Outline • Qualitative Description of CMOS Transistor • gm/ID Design • Biasing a transistor Using gm/ID Approach • Design Using Cadence

  3. A Crude Metal Oxide Semiconductor (MOS) Device V2 causes movement of negative charges, thus current. V1 can control the resistivity of the channel. Positive charge attract negative charges to interface between insulator and silicon. A conductive path is created If the density of electrons is sufficiently high. Q=CV. P-Type Silicon is slightly conductive. The gate draws no current!

  4. An Improved MOS Transistor (provide electrons) (drain electrons) n+ diffusion allows electrons move through silicon.

  5. Typical Dimensions of MOSFETs These diode must be reversed biased. tox is made really thin to increase C, therefore, create a strong control of Q by V.

  6. A Closer Look at the Channel Formulation Need to tie substrate to GND to avoid current through PN diode. VTH=300mV to 500 mV (OFF) (ON) Free electrons appear at VG=VTH. Positive charges repel the holes creating a depletion region, a region free of holes.

  7. Channel Resistance As VG increases, the density of electrons increases, the value of channel resistance changes with gate voltage.

  8. Drain Current as a function of Drain Voltage Resistance determined by VG.

  9. Drain Current as a function of Gate Voltage Higher VG leads to a lower channel resistance, therefore larger slope.

  10. Length Dependence The resistance of a conductor is proportional to the length.

  11. Dependence on Oxide Thickness Q=CV C is inversely proportional to 1/tox. Lower Q implies higher channel resitsance.

  12. Width Dependence The resistance of a conductor is inversely proportional to the cross section area. A larger device also has a larger capacitance!

  13. Channel Pinch Off • Q=CV • V=VG-VOXIDE-Silicon • VOXIDE-Silicon can change along the channel! Low VOXIDE-Silicon implies less Q.

  14. VG-VD is sufficiently large to produce a channel VG-VD is NOT sufficiently large to produce a channel No channel Electrons are swept by E to drain. Drain can no longer affect the drain current!

  15. Regions (No Dependence on VDS) No channel

  16. Determination of Region • How do you know whether a transistor is in the linear region or saturation region? • If VDS>(VGS-VTH) and VGS>VTH, then the device is in the saturation region. • If VDS<(VGS-VTH) and VGS>VTH, then the device is in the linear region.

  17. Graphical Illustration

  18. Limited VDS Dependence During Saturation As VDS increase, effective L decreases, therefore, ID increases.

  19. Pronounced Channel Length Modulation in small L

  20. Transconductance • As a voltage-controlled current source, a MOS transistor can be characterized by its transconductance: • It is important to know that

  21. What Happens to gm/ID when W and ID are doubled?

  22. Body Effect The threshold voltage will change when VSB=0!

  23. Experimental Data of Body Effect The threshold voltage will increase when VSB increases.

  24. Small Signal Model for NMOS Transistor

  25. PMOS Transistor

  26. IV Characteristics of a PMOS

  27. Small Signal Model of PMOS

  28. Small Signal Model of NMOS

  29. gm/ID Design Approach

  30. gm/ID Design Flow Specs Design Equations (Analytical) gm/Id Data Set (Emprical) gm/ID Design Optimization (F. Silveira, JSSC, 1996.) W/L Ratios

  31. Intuition gm gds gm/ID gm/gds 2gm 2gds gm/ID gm/gds 2gm 2gds gm/ID gm/gds

  32. gm/ID Data Set • gm/gds • gm/gmbs • ID/W • Cgd/Cgg • Cgs/Cgg • ….more (F. Silveira, JSSC, 1996.)

  33. Design Example

  34. Calculation Initially assume that gmro is large! (gm is determined)

  35. gm/gds (50)

  36. Current Density

  37. Biasing an MOS Transistor Using gm/ID technique Section 7.1 J.Ou Sonoma State Univeristy

  38. Basic Analysis Use 1.2 V (Modified Ex 7.1)

  39. Design Equations

  40. Assumption: VDD=1.2 V Transistor Information: Type: 120 nm Specify VDS Note var1_1 is ‘vsd’ if pmos is used Note var2_1 is ‘vns’ if nmos is used. In this example, is initially unknown, so we will assume that it is 0.0

  41. Interpolation Since the database base can not be so large as to keep all possible values of vds/vsb, we have to interpolate based on existing values, which are available On 0.1 V interval. Current release: need to enter inBias <= the minVar1 and maxVar1. minVar=maxVar-0.1

  42. Browse Database dBrowse2D(25, 'pfet', '15.0u', 'vsd', 0.3, 0.4, 0.353, 'vns', 0.5, 0.6, 0.577, 'vth') Variable name=dBrowse2D(gmoverid, type, length, var1, minVar1, maxVar1,inBias1, var2, minVar2, maxVar2,inBias2, ‘parameter’ ) Valid parameters: gmovergds, gmovergmbs, vth, ft, gmoveridft, idoverw, vod, region, fndbderiv cgdovercgg,cddovercgg, cgsovercgg, csbovercgg, cdbovercgg, ron, vdsat, rseff, rdeff type: nfet, pfet length: {'120n' '180n' '250n' '350n' '600n' '800n' '1.0u' '2.0u' '3.0u' '4.0u' '5.0u' '6.0u' '7.0u' '8.0u' '9.0u' '10.0u' '15.0u' '20.0u'} (text string)

  43. Iteration • Start with • length=‘120nm’ • gmoverid=20 • VDS=VDD/2, VSB=0 • Calculate • vod_1 • vth_ • vgs_1 • vx (gate voltage) • vs (source voltage) • ID • Idoverw • W • RD • Vd • Vds=Vd-Vs

  44. Iteration Example

  45. Design Iterations

  46. Matlab & Simulation

  47. Circuit Design Using Cadence J.Ou

  48. Start Cadence Start Cadence

  49. Create New Cellview

  50. Add Instance

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