Research of long distance clock distribution system

1. Research of long distance clock distribution system Université Libre de Bruxelles (IIHE) Yifan Yang, Kael Hanson, Aongus Ó Murchadha, Thomas Meures, Michael Korntheuer

2. OVERVIEW • Askaryan Radio Array background • Clock distribution over optical fiber based on low cost FPGA and jitter cleaner. • Fixed latency link implementation. • Conclusion and future plan. SEP 2012 TWEPP

3. Askaryan Radio Array background • Clock distribution over optical fiber based on low cost FPGA and jitter cleaner. • Fixed latency link implementation. • Conclusion and future plan. SEP 2012 TWEPP

4. Askaryan Radio Array 37 stations Spacing: 2 km Depth under ice surface: 200 m Surface coverage: ~160 km2 Ice thickness below: ~3000 m Each station: 16 + 4 sub-firn antennas (sensitive between 250 and 800 MHz):8 vertically polarized8 horizontally polarized 4 calibration pulsers (v-pol + h-pol) X surface antennas SEP 2012 TWEPP

5. Askaryan Radio Array • Current ARA uses analog optical fiber  • Easy, COTS (commercial off-the-shelf) item   • 1 antenna = 1 fiber => 4 fibers per hole  • slightly high power draw • price > 10 kEUR per station  • 4 ADC board on surface controlled by single processor board • Digital system • Custom designed • 4 antenna =1 fiber => 1 fiber per hole • Half the price • Extended communication system • 1 ADC board downhole controlled by one FPGA board • 50 ps skew stability is required in one station • 800Mbps data rate SEP 2012 TWEPP

6. Askaryan Radio Array background • Clock distribution over optical fiber based on low cost FPGA and jitter cleaner. • Fixed latency link implementation. • Conclusion and future plan. SEP 2012 TWEPP

7. Clock embedded in data • self-clocking signal SEP 2012 TWEPP

8. GTP To SFP From SFP Recovered clock is synchronized with transfer clock but with larger jitter SEP 2012 TWEPP

9. SI5368 Footprint compatible Interface compatible with on-surface processor board Generates any frequency from 2 kHz to 945 MHz Ultra-low jitter clock outputs with jitter generation as low as 300 fs rms (50 kHz–80 MHz) Integrated loop filter with selectable loop bandwidth  SEP 2012 TWEPP

10. Evaluation board and measurement setting After switching to recovered clock, a synchronized link is established System clock IRS2 Control module Spartan 6 lx45t with 4 GTPs SI5368 SEP 2012 TWEPP

11. Clock and data measurements SEP 2012 TWEPP

12. Latency measurements Before clock switching After clock switching SEP 2012 TWEPP

13. Clock skew measurement SEP 2012 TWEPP

14. Askaryan Radio Array background • Clock distribution over optical fiber based on low cost FPGA and jitter cleaner. • Fixed latency link implementation. • Conclusion and future plan. SEP 2012 TWEPP

15. Latency uncertain from GTP SEP 2012 TWEPP

16. Latency uncertain from GTP SEP 2012 TWEPP

17. Latency uncertain from jitter cleaner System clock IRS2 Control module Fixed phase difference between input and output of the jitter cleaner is also needed to establish a fixed latency link. Cdce62005 and LMK03200 both are used in new evaluation board. SEP 2012 TWEPP

18. New evaluation board and measurement setting Cdce62005(fixed delay) Lmk03200(0 delay) Spartan 6 lx45t with 4 GTPs SEP 2012 TWEPP

19. Clock skew measurement SEP 2012 TWEPP

20. Askaryan Radio Array background • Clock distribution over optical fiber based on low cost FPGA and jitter cleaner. • Fixed latency link implementation. • Conclusion and future plan. SEP 2012 TWEPP

21. Conclusion and future plan • Achieved: • Clock distribution over optical fiber • 50ps skew stability achieved • Latency of the link is kept in a certain range after power cycle on both direction • Things to do: • Long term, long distance, low temperature experiments • Automatic calibration • Remotely firmware upgrade • System optimum SEP 2012 TWEPP

22. Thank you! SEP 2012 TWEPP

23. backup SEP 2012 TWEPP

24. Clock separate with data transfer 250 meters standard cat5 cable SEP 2012 TWEPP