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DCS Detector Control System Hardware

DCS Detector Control System Hardware. Project Link http://www.kip.uni-heidelberg.de/ti/DCS-Board/current/. Introduction : DCS in the ALICE T ransition R adiation D etector. Dirk Gottschalk Volker Kiworra Volker Lindenstruth

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DCS Detector Control System Hardware

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  1. DCS Detector Control System Hardware Project Link http://www.kip.uni-heidelberg.de/ti/DCS-Board/current/ Introduction : DCS in the ALICE T ransitionR adiation D etector Dirk Gottschalk Volker Kiworra Volker Lindenstruth Vojtech Petracek Marc Stockmeier Heinz Tilsner Chair of Computer Science and Engineering / Prof. Dr. Volker Lindenstruth / http://www.kip.uni-heidelberg.de/ti/

  2. DCS Board Position in the TRD Chamber DCS Detector Control System Hardware Project Link http://www.kip.uni-heidelberg.de/ti/DCS-Board/current/ • One DCS Board controlls eight Read-Out Boards • Monitoring Functions : • Temperature Data from MCMs • Power Supply Data from MCMsSwitching Functions : • Shutdown for Voltage Regulators • Clock and Trigger Distribution Chair of Computer Science and Engineering / Prof. Dr. Volker Lindenstruth / http://www.kip.uni-heidelberg.de/ti/

  3. DCS Detector Control System Hardware DCS Interfaces Project Link http://www.kip.uni-heidelberg.de/ti/DCS-Board/current/ • Optical Clock Receiver Link (TTCrx) • Ethernet Link • Autonomous Power Supply • JTAG In and JTAG Out • 8 analog Inputs 16 Bit / 10Sps • 8 Pseudo LVDS Inputs • 8 Pseudo LVDS Outputs • 24 Switching Lines • two 8 Bit Ports ( optionaly ) • I²C Bus • Two Wire UART • optional CMC Connector ( if TTCrx is not used ) Chair of Computer Science and Engineering / Prof. Dr. Volker Lindenstruth / http://www.kip.uni-heidelberg.de/ti/

  4. DCS Board System Overview DCS Detector Control System Hardware Project Link http://www.kip.uni-heidelberg.de/ti/DCS-Board/current/ • Altera FPGA with ARM9 Core and 100k Gates • Ethernet Physikal Layer Chip • 32 MByte SDRAM • 4 MByte Flash EPROM • TTCrx Clock Recovery • 3.3 Volt and 1.8 Volt Voltage Regulators • RS422 Driver and Receiver for JTAG connections • LVDS Clock and Trigger Driver • Watchdog and Voltage Supervisor • 16 (24) Bit ADC with 10Sps Chair of Computer Science and Engineering / Prof. Dr. Volker Lindenstruth / http://www.kip.uni-heidelberg.de/ti/

  5. DCS Detector Control System Hardware DCS JTAG revitalisationsystem Project Link http://www.kip.uni-heidelberg.de/ti/DCS-Board/current/ A JTAG Master is implemented on DCS boards. This functionality ensures adjacent DCS board programmability in a dedicated JTAG Loop to repair inconsistent program or configuration data. Chair of Computer Science and Engineering / Prof. Dr. Volker Lindenstruth / http://www.kip.uni-heidelberg.de/ti/

  6. Board Layout DCS Detector Control System Hardware Project Link http://www.kip.uni-heidelberg.de/ti/DCS-Board/current/ Size 100x120mm Height 10,5mm max. Chair of Computer Science and Engineering / Prof. Dr. Volker Lindenstruth / http://www.kip.uni-heidelberg.de/ti/

  7. DCS Detector Control System Hardware Project Link http://www.kip.uni-heidelberg.de/ti/DCS-Board/current/ Chair of Computer Science and Engineering / Prof. Dr. Volker Lindenstruth / http://www.kip.uni-heidelberg.de/ti/

  8. Last but not least : DCS Detector Control System Hardware Project Link http://www.kip.uni-heidelberg.de/ti/DCS-Board/current/ • Project Status : 2003.02.14 • Schematic is final now.Preview : • Board will be routed next two weeks. • Prototypes will be likely available in april. Chair of Computer Science and Engineering / Prof. Dr. Volker Lindenstruth / http://www.kip.uni-heidelberg.de/ti/

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