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Structural Modeling: Entities Ports Architectures Packages

Structural Modeling: Entities Ports Architectures Packages. Ports and configurations, structures. VHDL Structure Description. Our goal is in next slides to explain the Component instantiation. describes basic hardware components and their interconnections via ports

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Structural Modeling: Entities Ports Architectures Packages

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  1. Structural Modeling: • Entities • Ports • Architectures • Packages

  2. Ports and configurations, structures

  3. VHDL Structure Description Our goal is in next slides to explain the Component instantiation • describes basic hardware components and their interconnections via ports • the basic features which should be defined: • component instantiation (includes regular structures), • ports interconnection and unconnected ports, • configuration (which entities and architectures are used to define components).

  4. Ports • ports in entity declarations • only signals are allowed of mode in, out, inout, buffer, • an example • • ports in component declarations • - only signals are allowed of mode in, out, inout, buffer, • an example

  5. Component Instantiation Statement label-identifier : component-mark generic mapassociation-list port mapassociation-list ; • an example Child : And2 port map (S1, S2, S3); • component instantiation statement performs association betweenlocaland actual port and checks the following rules: - the actual must be an object of class signal; • it can be defined as a signal declaration or may be a formal port declared in entity declaration, - the type of actual must be the same as the type of the local; if types are not the same a type conversion must be used. - signal modes must follow given requirements. • examples of a simple ALU, a decoder and a data bus.

  6. Default Component Binding • And-or structure build from standard NANDs

  7. Structural Architecture for and_or: an example • The correct code is this • In next slide we will see the circuit

  8. Let us compare the block diagram with the VHDL description In your homeworks, draw a diagram with all your names and explain the role of your gates and components

  9. Structural Architecture for and_or: an example: ARCHITECTURE STRUCTURE 2 • Architecture structure2 • Circuit in next slide

  10. Fast component for all

  11. Non-Default Component Binding

  12. Structural Architecture for and_or: an example • Architecture structure3 • Circuit in next slide

  13. Fast only for G3

  14. Default and Non-Default Port Binding

  15. Structural Architecture for and_or: an example • Architecture structure4

  16. Use of component inside an architecture structure4

  17. Configuration Specification: New Example A new example: configuration For U0

  18. Configuration Specification • allows the designer to specify the selection of entity declaration and architecture body for each component in-stance, • the general form of the configuration specification

  19. Non-Default Component Binding

  20. Default Values • if the signal is of a scalar subtype, • then the implicit default value of each driver is defined to be T'LEFT, where • T denotes the scalar subtype of the signal. • type ThreeValue is ('X', '0', '1'); • if the signal is of a composite subtype, • then each scalar subelement of the composite is a signal, • and each driver of each of these scalar subelements is defined to have an implicit default value by the previous rule. • default value can be specified explicitly in the declaration of the signal or port

  21. Default Values

  22. Unconnected Ports • any port of mode out, inout, or buffer may be unconnected provided its type is not an unconstrained array type; a port of mode in may be unconnected only if its declaration includes an explicit default expression. • the reserved word open indicates that a port is unconnected. • an example.

  23. Configuration Declaration • allows the designer to collect all of the binding information for the model into a single place- configuration specification.

  24. Structural Architecture for and_or: an example configuration Architecture structure5 has fast nand only for G3 and standard nand for G1 and G2

  25. Configuration Declaration • an example You can test behavior of various ready commercial chips working together

  26. Regular Structures • useful for describing hardware which is build of multiple instances of the same subcomponent connected in some regular pattern • it is done by the use of a generate statement label-identifier : generation-scheme generate concurrent-statements end generateidentifier ; • generation schemes: foridentifier in discrete-range ifboolean-expression • rules • the generate parameter (in for statement) acts as a constant, however, the generic parameter can be used, • there are no concurrent statements analogous to the sequential exit-statement and next-statement.

  27. Regular Structures- An Example

  28. Regular Structures- An Example • Generated Counter

  29. Configurations • Packages Do not be lost

  30. Sources • Prof. K. J. Hintz, Department of Electrical and Computer Engineering, George Mason University • Prof. John Wakerly, CISCO Systems and Stanford University. • Dr. Jose Nelson Amaral, University of Alberta • Krzysztof Kuchcinski • More information on ECE 271 class of Marek Perkowski.

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