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SOI Pixel Detector : Present Status & Future Plans

SOI Pixel Detector : Present Status & Future Plans. Super Belle Collb. Mtg Dec. 11, 2008 Yasuo Arai (KEK) yasuo.arai@kek.jp http://rd.kek.jp/project/soi/. [SOI Pixel Collaboration] KEK : Y. Unno, S. Terada, Y. Ikegami, T. Tsuboyama, T. Kohriki, K. Tauchi, Y. Ikemoto, T. Miyoshi, Y. Arai

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SOI Pixel Detector : Present Status & Future Plans

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  1. SOI Pixel Detector : Present Status & Future Plans Super Belle Collb. Mtg Dec. 11, 2008 Yasuo Arai (KEK) yasuo.arai@kek.jp http://rd.kek.jp/project/soi/ • [SOI Pixel Collaboration] • KEK : Y. Unno, S. Terada, Y. Ikegami, T. Tsuboyama, T. Kohriki, K. Tauchi, Y. Ikemoto, T. Miyoshi, Y. Arai • U. of Tsukuba : K. Hara, H. Miyake, M. Kouchiyama, T. Sega • Osaka U. : K. Hanagaki, M. Hirose • JAXA/ISAS : H, Ikeda, D. Kobayashi, T. Wada, H. Nagata • Tohoku U. : H. Yamamoto, Y. Takubo, T. Nagamine, Y. Horii, Y. Sato, • Kyoto U. : T. Tsuru • Riken/JASRI： T. Hatsui, T. Kudo, R. Ichimiya, A. Taketani • U. of Hawaii : G. Varner, J. Kennedy, M. Cooney, H. Hoedlmoser, E. Martin • LBNL : P. Denes, M. Battaglia, C. Vu, D. Contarato, P. Giubilato, L. Glesener • FNAL : R. Yarema, R. Lipton, G. Deptuch, M. Trimpl • OKI Elec. Ind. Co. Ltd. : M. Ohno, K. Fukuda, J. Ida, H. Hayashi, Y. Kawai, M. Okihara, H. Komatsubara, A. Ohtomo

  2. Introduction of SOI Pixel R&D SOI Pixel Test Results R&D Plans Summary OUTLINE

  3. Features of SOI Pixel Detector • Bonded wafer : High Resistivity (Sensor) + Low Resistivity (CMOS) . • Truly Monolithic Detector (-> High Density, Low material, Thin Device). • Standard CMOS can be used (-> Complex functions in a pixel). • No mechanical bonding (-> High yield, Low cost). • Fully depleted sensor with small capacitance of the sense node (~10fF, High conversion gain, Low noise) • Based on Industrial standard technology (-> Cost benefit and Scalability) • No Latch Up, Rad Hard. • Low Power • Low to High Temp(4K-300C) operation • ... 下部Siをセンサーとして利用

  4. KEK SOIPIX Target & Brief History Starting as a generic R&D program of KEK Detector Technology project in 2005. Main purposes are to establish a SOI Pixel process and develop pixel detectors for many applications. '05. 7: Start Collaboration with OKI Elec. Co. Ltd. '05.10: TEG submission to OKI SOI 0.15 mm process. '06.12: 1st 0.15 um MPW run hosted by KEK.(17 designs; KEK, Japanese Universities, LBNL, FNAL, U of Hawaii) '07.6: Process (and Fab.) is changed from 0.15 mm to 0.2 mm. '08.1: 1st 0.2 um KEK MPW run is submitted. '09.1: 2nd 0.2 um MPW run will be submitted. '09.6: 3rd 0.2um MPW run is planned.

  5. OKI 0.2 mm FD-SOI Pixel Process An example of a SOI Pixel cross section 5

  6. KEK SOI MPW run (2008.1)

  7. Integration Type Pixel (INTPIX) 128 x 128 pixels 5 x 5 mm2 20 mm x 20 mm pixel 7 7

  8. Counting Type Pixel Energy window and counting in each pixel. Dual Discri Counter 10.4 mm□ 128 x 128 pix Charge Amp

  9. CNTPIX2 Pixel Analog 16b Counter ~600 Transistors x 128 x 128 = 10,000,000 Trs p-n junctions 60x60 um2 9b Register DDL

  10. Super Belle pixel : SBPIX1 48x48 pixels 5x5 mm2 Modified from the CNTPIX2 Trigger Latency

  11. SOI Pixel Laser Images INTPIX2 2008 2.56 mm 2006 0.64 mm 32x32 128x128 11

  12. LBNL

  13. X-ray Irradiation Test X-ray Generator : Rigaku FR-D Target : Cu (Cu Ka ~8keV) Power : 30-35kV, 10-30mA (max 50kV,60mA) Intensity : ~104 photons/pixel/sec @30kV,10mA X-ray Tube SOI Pixel X-ray 13

  14. X-ray Test Chart Position resolution(pixel size=20mm x 20mm) INTPIX2 slit w=25mm 12.5 16 20 [lp/mm] 14 25 mm Slit is well separated.

  15. INTPIX2 Vdet=1.5V 800 ms Integration Time

  16. SBPIX1: X-ray Accumulated Image 16

  17. Position resolution(pixel size=60mm x 60mm) CNTPIX2 slit w=79.4mm 5 6.3 8 10 12.5 16 20 [lp/mm] Vdet=1.5V (~20 mm depletion) 1.6 ms Integration Time (~36 photons/pixel)

  18. SEABAS test board Ethernet INTPIX2 + Lens

  19. Max Readout Speed ~300 frames/sec (200 ns/pixel)

  20. R&D Plans Continue MPW runs : Number of the run will be increased twice/year. FY08 Submission : Feb. 2009 FY09 Submission : June and December 2009 + • Wafer Improvement : Double SOI wafer • Process Improvement : Implant through SOI layer • Implementation Improvement : 3D Integration

  21. SOI Wafer maker + OKI + KEK SOI Wafer R&D Introduce additional SOI Layer • Fix Potential under transistors • Less cross talk between circuits and sensors • Under evaluation at Japanese SOI wafer company.

  22. OKI + KEK SOI Process R&D n- Implant through SOI layer p p • Suppress back gate effect. • Reduce electric field around p+ sensor. • Less electric field in BOX to improve radiation hardness p+

  23. ZyCube + OKI + KEK/LBNL 3D R&D Use m-bump bonding (5~10 um pitch) technique. • SOI chips will be bonded by ZyCube. • Under design for Jan. '09 submission. • Will be bonded in Apr. '09.

  24. ZyCube + Tohoku Univ.

  25. Summary The SOI pixel has many good features (monolithic, low material, high speed ...) and a promising candidate for the future Super Belle pixel detector. Preliminary test chips are showing good response to light, b-rays, X-rays and charged particles. The number of the SOI MPW runs will be increased twice per year in 2009. We are doing several R&D ('Double SOI wafer', 'through SOI Implant', and '3D Integration' etc.) to get better performance in the SOI Pixel. There are still many items not to be tested. We welcome any people who have interests on the SOI pixel.

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