CSE241A VLSI Digital Circuits Winter 2003 Recitation 8: Project Midpoint Presentations

1. CSE241AVLSI Digital CircuitsWinter 2003Recitation 8: Project Midpoint Presentations

2. Group 6 Anuj Grover Puneet Sharma • Successfully added two AES core modules into the top level design • No syntactic errors found by DC • Synthesized the design successfully • Clock period = 5ns, all timings met • No scan FFs being added to design • Cell area reported = 513413.218750

3. Proj02 Stephen Cox Johnathan Wang • Goal A Total Optimization - Currently at Synthesis • Goal B Optimizing Area - Currently at Synthesis • Part A • Evaluation Method :Total Power x Clock Period x Total Area as given by Synthesis Reports • Most Promising Data • Run Comb Non Total Clk NetArea Effort • 5scr2 956K 89K 7272K 5ns 6226K HM • 6scr2a 981K 95K 7570K 3ns 6494K HM • 7scr2b 957K 95K 7409K 4ns 6357K HM

4. Proj02 Stephen Cox Johnathan Wang • Part B • Evaluation Method :Total Area as given by Synthesis Reports • Most Promising Data • Run Comb Non Total Clk NetArea Effort • 5scr2 956K 89K 7272K 5ns 6226K HM • SC2scr1 636K 84K 6558K 5ns 5837K HH • Phenomena • SC1scr1 636K 84K 721K 6558K 5ns 5837K HH (area limit=1000) • SC2scr1 636K 84K 721K 6558K 5ns 5837K HH (area limit=0)

5. Proj02 Stephen Cox Johnathan Wang • Things That Don’t Work • Do not set WLM between Compiles • Initial compile good, 2nd blows up area and timing. • Pass1 Area: 419502 in 2:50:55 Slack 0ns • Pass2 Area: 882371 in 14:37:29 Slack -4.20ns • Now ready to go to P&R with Pearl Script by Ben

6. Proj03 Budi Liong, Leslie Soka • We are still doing the synthesis of the area optimization. For part a, as we use the time constraint at 5 ns, then we need to optimize the area. We have achieved the timing constraint at that point. We also change some of the script to get better result on the optimization. For part B, we need to lower the timing constraint and we still figure out this part. We will do the place and route later of this day after we figure out about the place and route script.

7. 16th Order Digital FIR Project by A. Olsson and C.J. Lee • Problem Statement: • Synthesize, Place & Route three system architecture designs of a 16th order digital FIR filter. A tradeoff study with different arithmetic unit architecture and optimization metric will be analyzed and reported. Both system architecture and SP&R challenges will be addressed.

8. Schedule Progress: ≈1/4 System Complete (Behavior Architecture) 1/3 System Designed 1/3 System Tested 1/6 Design Synthesized 1/6 Design Place&Route 0/6 Design PrimeTime Check **RC, BK Adders / Array Multiplier Architecture Portion In Progress Milestones: 3/8-10 Complete Flow and Experiment Runs 3/11-12 Clean-up & Project Writing 3/13 Presentation Deadline: 3/14 Submit Deliverables Project Report 16th Order Digital FIR Project by A. Olsson and C.J. Lee

9. PartA: PDA objective Optimize for area and power change set_max_area yields poor results default 513183 #1 521855 PartB: Power objective Default: 886mW #1: 624mW #2(slack?) 578mW Proj10: Moonjung Kyung Weihaw Chuang • Summary: running synthesis on VlsiCad machines • Results from synopsys estimates

10. Proj01 Kavitha Kannan , Rekha Dili Babu • Our group (proj01) has chosen ‘Area optimization’ for part-B. So far, we have completed a few synthesis runs for part-a and part-b. We have not yet experimented with the power analysis for part-a. Here are the values for the different synthesis runs. We are still working on the synthesis script for part-a and part-b. • Part-A • Options Total cell Area Slack • 1. Default-given-script 400674.875000 (MET) - 44.71 • clk period - 50ns2. • 2. Default-given-script 513183.687500 (MET) - 00.03 • clkperiod – 5ns • 3. compile -incremental_mapping 505014.062500 (MET) – 00.02 • -map_effort high • -area_effort high • -boundary_optimization • -ungroup_all • 4. clock period 5ns 399703.562500 (MET) - 0.00 • compile with same options • as above • set max area 05. • 5. clock period 4.8 ns 402294.812500 (MET) - 0.00 • compile • with same options • as above • set max area 0

11. Proj01 Kavitha Kannan , Rekha Dili Babu • Part-B • OptionsTotal cell AreaSlack • 1. compile -map_effort low 400674.875000 MET - 4.53      • compile -area_effort high • 2. compile 405870.687500 (MET) - 0.01 • compile -map_effort high • 3. compile –map_effort high 413185.437500 (MET) - 0.01 • compile –map_effort high • 4. compile -map_effort high 391653.656250 (MET) - 0.00 set_max_area 0 • compile -area_effort high • 5. set_max_area 0 -ignore_tns 384931.000000 (MET) - 0.00 • compile -area_effort high • -map_effort high • 6. set_max_area 0 -ignore_tns 384931.000000 (MET) - 0.00 • set_cost_priority -area • compile -area_effort high • -map_effort high • 7. #set_flatten true • remove_constraint -all • set_max_area 0 • compile -area_effort high • -map_effort high 343094.875000 (Path is unconstrained) • 8. #set_flatten true 384931.000000 (MET) - 0.00 • set_max_area 0 • compile -area_effort high • -map_effort high • 9. #set_flatten true 386105.218750 MET - 0 • set_max_area 0 • compile -area_effort high  • -map_effort high • -ungroup_all • -boundary_optimization

12. PROJ07 KUMAR SAGAR PAVAN KUMAR PATIBANDA • Topic chosen for optimization : AREA Steps done :- • Top level verilog module encompassing two AES cores. • Synthesis using Synopsys Design Compiler, run with a tcl script. • Placement and routing using SE, run over netlist generated by DC. • So, part A is DONE ! • Working on part B (Area optimization). Target < 1 week.

13. PROJ07 KUMAR SAGAR PAVAN KUMAR PATIBANDA Sample synthesis results :- • Timing report Data required time 49.18 Data arrival time -4.56 Slack (MET) 44.62 • Area report Combinational area: 164039.734375 Noncombinational area: 36141.289062 Total cell area: 200179.421875 Thank You !