DO-254 Trends and Efficient Methods for Hardware Verification

1. DO-254 Trends and Efficient Methods for Hardware Verification MAPLD 2009 Presentation Session D: Design and Verification Tools and Methodologies

2. Agenda Introduction Challenges with Verification in Hardware for DO-254 DO-254/CTS Solution HDL Simulation In-Hardware Simulation with requirements traceability Hardware Output Validation Independent Tool Qualification Key Benefits of DO-254/CTS 2

3. Designing for DO-254 Compliance 3

4. Verification tool position in DO-254 compliant process Verification in Hardware with Requirements Traceability  Tool Qualification Process 4

5. Design Verification for DO-254 5 Let�s talk about Design Verification. Let me quote the specification. ....... That�s why it is not enough to use just the simulator, verification in hardware needs to be performed.Let�s talk about Design Verification. Let me quote the specification. ....... That�s why it is not enough to use just the simulator, verification in hardware needs to be performed.

6. Design Verification for DO-254 6 I think everybody will agree DO-254 design process is requirements driven process. Requirements are specified in Req Capture Process, after that stage HW Design Process is started (with Concept Level Design, Detailed Design and Implementation). Next verification process is started, natural way is HDL simulation, usually performed with Code Coverage Analysis. After that In-HW is executed. What Aldec proposes is using the same testbench (with already defined code coverage to drive the in-hw testing). This will allow to easily confirm the design meets the requirements with requirements traceability on each stage of verification.I think everybody will agree DO-254 design process is requirements driven process. Requirements are specified in Req Capture Process, after that stage HW Design Process is started (with Concept Level Design, Detailed Design and Implementation). Next verification process is started, natural way is HDL simulation, usually performed with Code Coverage Analysis. After that In-HW is executed. What Aldec proposes is using the same testbench (with already defined code coverage to drive the in-hw testing). This will allow to easily confirm the design meets the requirements with requirements traceability on each stage of verification.

7. RTL, Netlist and Timing Simulation Simulation is driven by the set of testbenches Results are stored in the signal database files (waveforms, etc) Simulation levels tested Functional simulation Gate-level netlist simulation Timing simulation All tested levels reuse the same testbenches 7 Let�s talk about HDL simulation. How it works. Simulation is driven .... Of course all those features are available in Aldec�s simulators.Let�s talk about HDL simulation. How it works. Simulation is driven .... Of course all those features are available in Aldec�s simulators.

8. Analysis Tools Complementing HDL Simulation Code Coverage Line and Branch coverage Toggle coverage Expression coverage Code Linting Coding Styles rules Design Style rules Synthesis rules 8 As an addititon Analysis Tools are available, Aldec�s simulators Active-HDL and Riviera-PRO are equipped with Code CoVerage and Code Linting.As an addititon Analysis Tools are available, Aldec�s simulators Active-HDL and Riviera-PRO are equipped with Code CoVerage and Code Linting.

9. Traditional Testing in Hardware Real-time stimuli are streaming through the design inputs Design outputs (FPGA) are connected to another discrete components on the board 9 Let�s move to Testing in Hardware. What is traditional way of testing in hardware? Design is implemented in target hardware, real-time data are driving the design inputs, FPGA outputs are connected to another part of the system or connecters. What kind of challenges appear in this process.Let�s move to Testing in Hardware. What is traditional way of testing in hardware? Design is implemented in target hardware, real-time data are driving the design inputs, FPGA outputs are connected to another part of the system or connecters. What kind of challenges appear in this process.

10. In-Hardware Simulation at Target Speed 10 Note, it is good to mention that Input and Golden Vectors should be reviewed and analyzed at this point to be sure the input data for in-hw sim is correct and results pattern is correct.Note, it is good to mention that Input and Golden Vectors should be reviewed and analyzed at this point to be sure the input data for in-hw sim is correct and results pattern is correct.

11. In-Hardware Simulation at Target Speed 11

12. Hardware Output Validation Visual analysis of hardware recorded waveforms Comparing hardware output with RTL (golden) output graphically as waveform files as two text files 12

13. DO-254/CTS Hardware Architecture 13

14. DO-254/CTS Practical Application 14

15. Tool Assessment and Qualification Process 15

16. Independent Tool Assessment with DO-254/CTS Comparing output of RTL and HW simulations Validates RTL simulation results Validates Hardware simulation results * In addition, set of the hardware diagnostic tests is provided to qualify Aldec�s hardware simulation tool 16

17. Summary: DO-254 CTS 17 Let�s summarize, what are you getting with Aldec/DO-254 CTS?Let�s summarize, what are you getting with Aldec/DO-254 CTS?