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Design a MIPS Processor

Design a MIPS Processor. Instruction set overview of MIPS processors Single cycle MIPS processor Datapath design Controller design Multiple cycle MIPS Processor Datapath design Controller design finite state machine; sequencer; microcode.

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Design a MIPS Processor

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  1. Design a MIPS Processor • Instruction set overview of MIPS processors • Single cycle MIPS processor • Datapath design • Controller design • Multiple cycle MIPS Processor • Datapath design • Controller design • finite state machine; sequencer; microcode. • Design a Multiple cycle MIPS Processor with Verilog at Behavioral/Structural Level (Project 5)

  2. MIPS ISA as an Example Registers • Instruction categories: • Load/Store • Computational • Jump and Branch • Floating Point • Memory Management • Special $r0 - $r31 PC 3 Instruction Formats: all 32 bits wide R type I type Jump OP $rs $rd sa funct $rt immediate OP $rs $rt jump target OP

  3. 6 5 5 5 5 6 opcode rs rt rd shamt funct R-Format Instructions • opcode: partially specifies what the instruction is (Note: 0 for all R-Format instructions) • funct: combined with opcode to specify the instruction • rs (Source Register): specify register containing first operand • rt (Target Register): specify register containing second operand • rd (Destination Register): specify register which will receive result of computation

  4. MIPS Arithmetic Instructions • MIPS assembly language arithmetic statement add $r10, $r11, $r12 sub $r10, $r11, $r12 • Each arithmetic instruction performs only one operation • Each arithmetic instruction fits in 32 bits and specifies exactly three operands destination  source1 op source2 • Those operands are all contained in the datapath’s register file ($r10,$r11,$r12) – indicated by $ • Operand order is fixed (destination first)

  5. MIPS Memory Access Instructions • MIPS has two basic data transfer instructions for accessing memory lw $t0, 4($s3) #load word from memory sw $t0, 8($s3) #store word to memory • The data is loaded into (lw) or stored from (sw) a register in the register file – a 5-bit address • The memory address – a 32-bit address – is formed by adding the contents of the base address register to the offset value • A 16-bit field meaning access is limited to memory locations within a region of 213 or 8,192 words (215 or 32,768 bytes) of the address in the base register • Note that the offset can be positive or negative

  6. MIPS Data Transfer Instructions InstructionComment sw $t3,500($t4) Store word sh $t3,502($t2) Store half sb $t2,41($t3) Store byte lw $t1, 30($t2) Load word lh $t1, 40($t3) Load halfword lhu $t1, 40($t3) Load halfword unsigned lb $t1, 40($t3) Load byte lbu $t1, 40($t3) Load byte unsigned lui $t1, 40 Load Upper Immediate (16 bits shifted left by 16)

  7. op rs rt 16 bit offset MIPS Control Flow Instructions • MIPS conditional branch instructions: bne $s0, $s1, Lbl #go to Lbl if $s0$s1 beq $s0, $s1, Lbl #go to Lbl if $s0=$s1 • Ex: if (i==j) h = i + j; bne $s0, $s1, Lbl1 add $s3, $s0, $s1Lbl1: ... • Instruction Format (I format): • How is the branch destination address specified?

  8. from the low order 16 bits of the branch instruction 16 offset sign-extend 00 branch dst address 32 32 Add PC 32 32 Add 32 ? 4 32 32 Specifying Branch Destinations • Use a register (like in lw and sw) added to the 16-bit offset • which register? Instruction Address Register (the PC) • its use is automatically implied by instruction • PC gets updated (PC+4) during the fetch cycle so that it holds the address of the next instruction • limits the branch distance to -215 to +215-1 instructions from the (instruction after the) branch instruction

  9. op 26-bit address from the low order 26 bits of the jump instruction 26 00 32 4 PC 32 Other Control Flow Instructions • MIPS also has an unconditional branch instruction or jump instruction:j label //go to label • Instruction Format (J Format):

  10. I format op rs rt 16 bit immediate MIPS Immediate Instructions • Small constants are used often in typical code addi $sp, $sp, 4 //$sp = $sp + 4 slti $t0, $s2, 15 //$t0 = 1 if $s2<15 • Machine format (I format): • The constant is kept inside the instruction itself! • Immediate format limits values to the range +215–1 to -215 more MIPS immediate Instructions: addi $r29, $r29, 4 slti $r8, $r18, 10 andi $r29, $r29, 6 ori $r29, $r29, 4 addi $r10,$r111,10

  11. 000000 01001 01010 01000 00000 100000 R-Format Example • MIPS Instruction: add $8,$9,$10 • opcode = 0 (look up in table) • funct = 32 (look up in table) • rs = 9 (first operand) • rt = 10 (second operand) • rd = 8 (destination) • shamt = 0 (not a shift) binary representation:

  12. 001000 8 10110 22 10101 21 1111111111001110 -50 I-Format Example 1 • MIPS Instruction: addi $21,$22,-50 • opcode = 8 (look up in table) • rs = 22 (register containing operand) • rt = 21 (target register) • immediate = -50 (by default, this is decimal) decimal representation: binary representation:

  13. 100011 35 01001 9 01000 8 0000010010110000 1200 I-Format Example 2 • MIPS Instruction: lw $8,1200($9) • opcode = 35 (look up in table) • rs = 9 (base register) • rt = 8 (destination register) • immediate = 1200 (offset) decimal representation: binary representation:

  14. 31 26 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits op 31 26 21 16 0 address 6 bits 26 bits Our Example: A MIPS Subset • R-Type: • add rd, rs, rt • sub rd, rs, rt • and rd, rs, rt • or rd, rs, rt • slt rd, rs, rt • Load/Store: • lw rt,rs,imm16 • sw rt,rs,imm16 • Imm operand: • addi rt,rs,imm16 • Branch: • beq rs,rt,imm16 • Jump: • j target

  15. Register Transfers • RTL gives the meaning of the instructions • All start by fetching the instruction, read registers, then use ALU . memory access, write results. MEM[ PC ] = op | rs | rt | rd | shamt | funct or = op | rs | rt | Imm16 or = op | Imm26 Inst Register transfers ADD R[rd] <- R[rs] + R[rt]; PC <- PC + 4 SUB R[rd] <- R[rs] - R[rt]; PC <- PC + 4 LOAD R[rt] <- MEM[ R[rs] + sign_ext(Imm16)]; PC <- PC + 4 STORE MEM[ R[rs] + sign_ext(Imm16) ] <-R[rt]; PC <- PC + 4 ADDI R[rt] <- R[rs] + sign_ext(Imm16); PC <- PC + 4 BEQ if (R[rs] == R[rt]) then PC <- PC + 4 + sign_ext(Imm16) || 00 else PC <- PC + 4

  16. Requirements of the Datapath After checking the register transfers, we can see that datapath needs the followings: • Memory • store instructions and data • Registers (32 x 32) • read RS • read RT • Write RT or RD • PC • Extender for zero- or sign-extension • Add and sub register or extended immediate (ALU) • Add 4 or extended immediate to PC

  17. Datapath Components • Basic building blocks of combinational logic elements : CarryIn Select A 32 A 32 Sum Adder MUX 32 Y 32 B Carry B 32 32 MUX Adder ALU control A 32 Result ALU 32 B 32 ALU

  18. Datapath Components Storage elements: • Register: • Similar to the D Flip Flop except • N-bit input and output • Write Enable input • Write Enable: • negated (0): Data Out will not change • asserted (1): Data Out will become Data In Write Enable Data In Data Out N N Clk

  19. Register File RW RA RB Write Enable • Consists of 32 registers: • Two 32-bit output busses: busA and busB • One 32-bit input bus: busW • Register is selected by: • RA selects the register and puts the content on busA (data) • RB selects the register and puts the content on busB (data) • RW selects the register to be written via busW (data) when Write Enable is 1 • Clock input (CLK) • Can have other control signals in your design • such as read, write, etc 5 5 5 busA busW 32 32-bit Registers 32 busB Clk 32

  20. Clocking Methodologies • The clocking methodology defines when signals can be read and when they are written • An edge-triggered methodology • Typical execution • read contents of state elements • send values through combinational logic • write results to one or more state elements State element 1 State element 2 Combinational logic clock one clock cycle • Assumes state elements are written on every clock cycle; if not, need explicit write control signal • write occurs only when both the write control is asserted and the clock edge occurs

  21. Fetching Instructions • Fetching instructions involves • reading the instruction from the Instruction Memory • updating the PC to hold the address of the next instruction Add 4 Instruction Memory Read Address Instruction PC • PC is updated every cycle, so it does not need an explicit write control signal • Instruction Memory is read every cycle, so it doesn’t need an explicit read control signal

  22. Read Addr 1 Read Data 1 Register File Read Addr 2 Write Addr Read Data 2 Write Data Decoding Instructions • Decoding instructions involves • sending the fetched instruction’s opcode and function field bits to the control unit Control Unit Instruction • reading two values from the Register File • Register File addresses are contained in the instruction

  23. 31 25 20 15 10 5 0 R-type: op rs rt rd shamt funct Executing R Format Operations • R format operations (add, sub, slt, and, or) • perform the (op and funct) operation on values in rs and rt • store the result back into the Register File (into location rd) RegWrite ALU control Read Addr 1 Read Data 1 Register File Read Addr 2 overflow Instruction zero ALU Write Addr Read Data 2 Write Data • The Register File is not written every cycle (e.g. sw), so we need an explicit write control signal for the Register File

  24. RegWrite ALU control MemWrite overflow zero Read Addr 1 Read Data 1 Address Register File Read Addr 2 Instruction Data Memory Read Data ALU Write Addr Read Data 2 Write Data Write Data MemRead Sign Extend 16 32 Executing Load and Store Operations • Load and store operations involves • compute memory address by adding the base register (read from the Register File during decode) to the 16-bit signed-extended offset field in the instruction • store value (read from the Register File during decode) written to the Data Memory • load value, read from the Data Memory, written to the Register File

  25. Executing Branch Operations • Branch operations involves • compare the operands read from the Register File during decode for equality (zero ALU output) • compute the branch target address by adding the updated PC to the 16-bit signed-extended offset field in the instr Add Branch target address Add 4 Shift left 2 ALU control PC zero (to branch control logic) Read Addr 1 Read Data 1 Register File Read Addr 2 Instruction ALU Write Addr Read Data 2 Write Data Sign Extend 16 32

  26. Executing Jump Operations • Jump operation involves • replace the lower 28 bits of the PC with the lower 26 bits of the fetched instruction shifted left by 2 bits Add 4 4 Jump address Instruction Memory Shift left 2 28 Read Address PC Instruction 26

  27. Creating a Single Datapath from the Parts • Assemble the datapath segments and add control lines and multiplexors as needed • Single cycle design – fetch, decode and execute each instructions in one clock cycle • no datapath resource can be used more than once per instruction, so some must be duplicated (e.g., separate Instruction Memory and Data Memory, several adders) • multiplexors needed at the input of shared elements with control lines to do the selection • write signals to control writing to the Register File and Data Memory • Cycle time is determined by length of the longest path

  28. Add RegWrite ALUSrc ALU control MemWrite MemtoReg 4 ovf zero Read Addr 1 Instruction Memory Read Data 1 Address Register File Read Addr 2 Data Memory Read Address PC Instruction Read Data ALU Write Addr Read Data 2 Write Data Write Data MemRead Sign Extend 16 32 Fetch, Register File, and Memory Access Portions

  29. 31 25 0 J-type: op target address Adding the Control • Selecting the operations to perform (ALU, Register File and Memory read/write) • Controlling the flow of data (multiplexor inputs) 31 25 20 15 10 5 0 R-type: op rs rt rd shamt funct 31 25 20 15 0 I-Type: address offset op rs rt • Observations • op field always in bits 31-26 • addr of registers to be read are always specified by the rs field (bits 25-21) and rt field (bits 20-16); for lw and sw rs is the base register • addr. of register to be written is in one of two places – in rt (bits 20-16) for lw; in rd (bits 15-11) for R-type instructions • offset for beq, lw, and sw always in bits 15-0

  30. Single Cycle Datapath with Control Unit 0 Add Add 1 4 Shift left 2 ALUOp PCSrc Branch MemRead Instr[31-26] Control Unit MemtoReg MemWrite ALUSrc RegWrite RegDst ovf Instr[25-21] Read Addr 1 Instruction Memory Read Data 1 Address Register File Instr[20-16] zero Read Addr 2 Data Memory Read Address PC Instr[31-0] 0 Read Data 1 ALU Write Addr Read Data 2 0 1 Write Data 0 Instr[15 -11] Write Data 1 Instr[15-0] Sign Extend ALU control 16 32 Instr[5-0]

  31. R-type Instruction Data/Control Flow 0 Add Add 1 4 Shift left 2 PCSrc ALUOp Branch MemRead Instr[31-26] Control Unit MemtoReg MemWrite ALUSrc RegWrite RegDst ovf Instr[25-21] Read Addr 1 Instruction Memory Read Data 1 Address Register File Instr[20-16] zero Read Addr 2 Data Memory Read Address PC Instr[31-0] 0 Read Data 1 ALU Write Addr Read Data 2 0 1 Write Data 0 Instr[15 -11] Write Data 1 Instr[15-0] Sign Extend ALU control 16 32 Instr[5-0]

  32. Load Word Instruction Data/ControlFlow 0 Add Add 1 4 Shift left 2 PCSrc ALUOp Branch MemRead Instr[31-26] Control Unit MemtoReg MemWrite ALUSrc RegWrite RegDst ovf Instr[25-21] Read Addr 1 Instruction Memory Read Data 1 Address Register File Instr[20-16] zero Read Addr 2 Data Memory Read Address PC Instr[31-0] 0 Read Data 1 ALU Write Addr Read Data 2 0 1 Write Data 0 Instr[15 -11] Write Data 1 Instr[15-0] Sign Extend ALU control 16 32 Instr[5-0]

  33. Load Word Instruction Data/Control Flow 0 Add Add 1 4 Shift left 2 PCSrc ALUOp Branch MemRead Instr[31-26] Control Unit MemtoReg MemWrite ALUSrc RegWrite RegDst ovf Instr[25-21] Read Addr 1 Instruction Memory Read Data 1 Address Register File Instr[20-16] zero Read Addr 2 Data Memory Read Address PC Instr[31-0] 0 Read Data 1 ALU Write Addr Read Data 2 0 1 Write Data 0 Instr[15 -11] Write Data 1 Instr[15-0] Sign Extend ALU control 16 32 Instr[5-0]

  34. Branch Instruction Data/Control Flow 0 Add Add 1 4 Shift left 2 PCSrc ALUOp Branch MemRead Instr[31-26] Control Unit MemtoReg MemWrite ALUSrc RegWrite RegDst ovf Instr[25-21] Read Addr 1 Instruction Memory Read Data 1 Address Register File Instr[20-16] zero Read Addr 2 Data Memory Read Address PC Instr[31-0] 0 Read Data 1 ALU Write Addr Read Data 2 0 1 Write Data 0 Instr[15 -11] Write Data 1 Instr[15-0] Sign Extend ALU control 16 32 Instr[5-0]

  35. Branch Instruction Data/Control Flow 0 Add Add 1 4 Shift left 2 PCSrc ALUOp Branch MemRead Instr[31-26] Control Unit MemtoReg MemWrite ALUSrc RegWrite RegDst ovf Instr[25-21] Read Addr 1 Instruction Memory Read Data 1 Address Register File Instr[20-16] zero Read Addr 2 Data Memory Read Address PC Instr[31-0] 0 Read Data 1 ALU Write Addr Read Data 2 0 1 Write Data 0 Instr[15 -11] Write Data 1 Instr[15-0] Sign Extend ALU control 16 32 Instr[5-0]

  36. Adding the Jump Operation Instr[25-0] 1 Shift left 2 28 32 26 0 PC+4[31-28] 0 Add Add 1 4 Shift left 2 PCSrc Jump ALUOp Branch MemRead Instr[31-26] Control Unit MemtoReg MemWrite ALUSrc RegWrite RegDst ovf Instr[25-21] Read Addr 1 Instruction Memory Read Data 1 Address Register File Instr[20-16] zero Read Addr 2 Data Memory Read Address PC Instr[31-0] 0 Read Data 1 ALU Write Addr Read Data 2 0 1 Write Data 0 Instr[15 -11] Write Data 1 Instr[15-0] Sign Extend ALU control 16 32 Instr[5-0]

  37. Cycle 1 Cycle 2 Clk lw sw Waste Single Cycle Disadvantages & Advantages • Uses the clock cycle inefficiently – the clock cycle must be timed to accommodate the slowest instruction • especially problematic for more complex instructions like floating point multiply • May be wasteful of area since some functional units (e.g., adders) must be duplicated since they can not be shared during a clock cycle but • Is simple and easy to understand

  38. Multicycle Datapath Approach • Let an instruction take more than 1 clock cycle to complete • Break up instructions into steps where each step takes a cycle while trying to • balance the amount of work to be done in each step • restrict each cycle to use only one major functional unit • Not every instruction takes thesame number of clock cycles • In addition to faster clock rates, multicycle allows functional units that can be used more than once per instruction as long as they are used on different clock cycles, as a result • only need one memory – but only one memory access per cycle • need only one ALU/adder – but only one ALU operation per cycle

  39. IR Address Memory A Read Addr 1 PC Read Data 1 Register File Read Addr 2 Read Data (Instr. or Data) ALUout ALU Write Addr Write Data Read Data 2 B Write Data MDR Multicycle Datapath Approach • At the end of a cycle • Store values needed in a later cycle by the current instruction in an internal register (not visible to the programmer). All (except IR) hold data only between a pair of adjacent clock cycles (no write control signal needed) IR – Instruction Register MDR – Memory Data Register A, B – regfile read data registers ALUout – ALU output register • Data used by subsequent instructions are stored in programmer visible registers (i.e., register file, PC, or memory)

  40. MDR The Multicycle Datapath with Control Signals PCWriteCond PCWrite PCSource IorD ALUOp MemRead Control ALUSrcB MemWrite ALUSrcA MemtoReg RegWrite IRWrite RegDst PC[31-28] Instr[31-26] Shift left 2 28 Instr[25-0] 2 0 1 Address Memory 0 PC 0 Read Addr 1 A Read Data 1 IR Register File 1 1 zero Read Addr 2 Read Data (Instr. or Data) 0 ALUout ALU Write Addr Write Data 1 Read Data 2 B 0 1 Write Data 4 1 0 2 Instr[15-0] Sign Extend Shift left 2 3 32 ALU control Instr[5-0]

  41. Datapath control points Combinational control logic . . . . . . . . . State Reg Inst Opcode Next State Multicycle Control Unit • Multicycle datapath control signals are not determined solely by the bits in the instruction • e.g., op code bits tell what operation the ALU should be doing, but not what instruction cycle is to be done next • Must use a finite state machine (FSM) for control • a set of states (current state stored in State Register) • next state function (determined by current state and the input) • output function (determined by current state and the input)

  42. IFetch Exec Mem WB The Five Steps of the Load Instruction Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Dec lw • IFetch: Instruction Fetch and Update PC • Dec: Instruction Decode, Register Read, Sign Extend Offset • Exec: Execute R-type; Calculate Memory Address; Branch Comparison; Branch and Jump Completion • Mem: Memory Read; Memory Write Completion; R-type Completion (RegFile write) • WB: Memory Read Completion (RegFile write) INSTRUCTIONS TAKE FROM 3 - 5 CYCLES

  43. Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 Clk lw sw R-type IFetch Dec Exec Mem WB IFetch Dec Exec Mem IFetch Multicycle Advantages & Disadvantages • Uses the clock cycle efficiently – the clock cycle is timed to accommodate the slowest instruction • Multicycle implementations allow functional units to be used more than once per instruction as long as they are used on different clock cycles but • Requires additional internal state registers, more muxes, and more complicated (FSM) control

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