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CSC Muon Trigger - Annual Review

CSC Muon Trigger - Annual Review. Jay Hauser, with many slides from Darin Acosta and Stan Durkin Personnel: Professors Darin Acosta (Florida), Robert Cousins (UCLA), Jay Hauser (UCLA), Paul Padley (Rice), Jaybus Roberts (Rice) Postdocs

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CSC Muon Trigger - Annual Review

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  1. CSC Muon Trigger - Annual Review Jay Hauser, with many slides from Darin Acosta and Stan Durkin Personnel: • Professors • Darin Acosta (Florida), Robert Cousins (UCLA), Jay Hauser (UCLA), Paul Padley (Rice), Jaybus Roberts (Rice) • Postdocs • Sang-Joon Lee (Rice), Holger Stoeck (Florida), Slava Valouev (UCLA), Martin von der Mey (UCLA), Song Ming Wang (Florida), Yangheng Zheng (UCLA) • Students • Alexei Drozdertski (Florida), Brian Mohr (UCLA), Jason Mumford (UCLA), Greg Pawloski (Rice), Bobby Scurlock (Florida), • Engineers • JK Smith (UCLA), Alex Madorsky (Florida), Mike Matveev (Rice), Ted Nussbaum (Rice), Alex Tumanov (Rice - Software) • Collaborating engineers (PNPI) • Victor Golovtsov, Valeri Iatsioura, Lev Uvarov Outline: • Status of Boards • Test Beam 2003 Results • Experience and Plans for Production Testing • Plans for Integration and Slice Tests • Schedule and Milestones CMS Annual Review

  2. Current Status of CSC Trigger Elements – Quick Summary • On-chamber • Comparator ASICs for Cathodes (CFEB cards) – DONE. • ALCT Anode Trigger – almost done (~90%) • Peripheral-crate • TMB Trigger Motherboard – pre-production prototypes • MPC Muon Port Card – 2nd generation prototype • CCB Clock & Control Board – 2nd generation prototype • Track Finder crate in counting house • SP2002 Sector Processor – 2nd generation prototype • CSC Muon Sorter – 1st generation prototype • Backplane – 2nd generation prototype CMS Annual Review

  3. D M B T M B D M B T M B D M B T M B D M B T M B D M B T M B C C B M P C T M B D M B T M B D M B T M B D M B T M B D M B C O N T R O L L E R 1 of 5 1 of 5 Cathode Front-end Board CFEB CFEB CFEB CFEB CFEB 1 of 2 1 of 24 ALCT LVDB Anode Front-end Board CSC CSC Muon Trigger Scheme EMU part: on-chamber nearing end of production, peripheral crate production > ESR in Nov. ‘03 TriDAS part: Second generation prototypes Muon Portcard (1) Trigger Motherboard (9) Clock Control Board Trigger Timing & Control DAQ Motherboard (9) Optical link Peripheral Crate on iron disk (1 of 60) Muon Sorter (1) Sector Processor (12) CSC Track-Finder Crate (1) Anode LCT Board In underground counting room On detector Trigger Primitives 3-D Track-Finding and Measurement CMS Annual Review

  4. On-chamber CSC Trigger Electronics • Comparator ASICs – DONE. • Compare pulse heights from adjacent strips to find position of muon to ½-strip • 15000 16-channel ASICS on CFEB boards (OSU) • ALCT Boards – nearly DONE. • Finds tracks among anode hits, stores data for readout • 468+spares boards of 3 types (288-, 384-, 672-channel) CMS Annual Review

  5. C C B D M B T M B D M B T M B D M B T M B D M B T M B D M B T M B M P C T M B D M B T M B D M B T M B D M B T M B D M B C O N T R O L L E R CSC Peripheral Crates in UXC55 Crate Controller DAQ Motherboard (DMB) TRIG Motherboard (TMB) Muon Port Card (MPC) Clock Control Board (CCB) CMS Annual Review

  6. Trigger Motherboard • Generates Cathode LCT and matches ALCT with CLCT • Prototyped 18 TMB2001 with XCV1000E (15 for chamber testing). • 4 new TMB2003 prototypes with “production engineering” and XC2V4000. • Nov. ’03 ESR should lead into production cycle in ‘04. • 468 boards 9U x 400mm required for CSC trigger UCLA CFEB Input connectors Mezzanine board ALCT input connectors CMS Annual Review

  7. Common design for both Peripheral and Track-Finder crates 20 Boards exist Have been distributed and used for chamber testing 60+1 required for CMS operation Clock and Control Board Mezzanine card with PLD TTCrx Mezzanine Card Rice ECL inputs ECL outputs 9U * 400 MM BOARD CMS Annual Review

  8. Sorts up to 18 LCTs from 9 chambers and transmits best 3 to Track-Finder crate 6 Boards of second generation have been fabricated and assembled. Board has passed standalone tests, communication tests with TMB, and cosmic ray tests Successfully read data from 2 chambers and sorted correctly Tests with Track-Finder are continuing Tests in time-structured test beam are underway now (for second time this year) 60 required for CMS operation Muon Port Card Rice TLK2501 serializers Mezzanine card (same as TMB design) Optomodules (1.6 Gbit/s) CMS Annual Review

  9. 1st Prototype Track-Finder Tests Clock Control Board (Rice) Sector Receiver (UCLA) Muon Port Card (Rice) Sector Processor (Florida) SBS VME Interface Very successful, but overall CSC latency was too long New 2002 design improves latency, reduces # of crates from 6 to 1 Custom ChannelLink Backplane (Florida) Results included in Trigger TDR (2000) CMS Annual Review

  10. CSC Track-Finder Crate Second generation prototypes Sector Receiver/Processor Clock and Control Board SR SR SR SR SR SR SR SR SR SR SR SR CCB MS / / / / / / / / / / / / SP SP SP SP SP SP SP SP SP SP SP SP From MPC SBS 620 Controller (chamber 4) Muon Sorter From MPC (chamber 3) From MPC (chamber 2) From MPC (chamber 1B) From MPC (chamber 1A) To DAQ Single Track-Finder Crate Design with 1.6 Gbit/s optical links Custom 6U GTLP backplane for interconnections CMS Annual Review

  11. 12 Used in CMS System SP2002 (Main Board) Receiver: Florida • Optical Transceivers • 16 x 1.6 Gbit/s Links VME/CCB FPGA TLK2501 Transceiver Data conversion: Phi Global LUT To/from custom GTLP back-plane Eta Global LUT Phi Local LUT Merged 3 SR2000s Front FPGA CMS Annual Review

  12. SP Trigger Logic From SP2000 to SP2002 mezzanine card (5 manufactured) Florida Xilinx Virtex-2 XC2V4000~800 user I/O Performs track-finding logic and PT assignment CMS Annual Review

  13. Sorts up to 36 muons from 12 SP’s and transmits best 4 to GMT Have 4 boards in hand, one stuffed (except for backplane interface) Sorter testing is in progress, will test with Track-Finder in the autumn Only 1 needed in CMS Muon Sorter Rice MEZZANINE CARD (same as SP design) LVDS DRIVERS AND SCSI-3 CONNECTORS GTLP BACKPLANE INTERFACE CMS Annual Review

  14. CSC Test Beam Studies 2003 • First structured beam period May 23-June 1 • Trigger primitives tests were highly successful: • Reliable high-rate trigger and DAQ system • ALCT timing tests, CLCT and TMB studies • High-rate tests and HV, threshold, angle scans • MPC-to-SP optical link data transfer unsuccessful (synch. problems) • Unstructured beam period June 13-28 • Improved low- and high-rate CLCT and TMB studies, angle scans • Second structured beam period Sept. 17-22 • Patches to fix optical link data transfer from MPC to SP • New readout shell program (fully OO software) CMS Annual Review

  15. X5A Setup 2003 Time-structured Beam Test Setup TTC crate Trigger primitives DAQ Data PC Peripheral Crate 2 DMB, 2 TMB 1 CCB, 1 MPC FED crate 1 DDU Track finder Crate TRIDAS beam S1 S3 S2 CSC 2 CSC 1 CMS Annual Review

  16. Raw data includes 8 or 16 time bins history Typical Muon Event CMS Annual Review

  17. 1.2 ms 23 ms SPS orbit period 2003 Time-Structured Test Beam • Optimal timing found • High efficiency (~98-99%) achieved • Peripheral crate system basically working as desired • Small CLCT efficiency loss at high rates, almost no ALCT efficiency loss 48 bunches 25 ns bunch spacing bunch width 3-5 ns Scintillation Counters 48 bunches ALCT Structure repeats during 2.6 s spill length CMS Annual Review BX Number

  18. CSC Bunch ID From ALCT Timing • First, tune the ALCT data latching in 2 ns intervals (0-32ns) and maximize the single-BX fraction of events: • Then look at the BX distribution relative to BX from scintillator (L1A): • ALCT BX efficiency 98.7% CMS Annual Review

  19. CLCT Positions • Key CLCT half strip from chamber 2 vs.1: • On fine scale “staircase” structure indicates good trigger position resolution • (note that chamber 1 is vertically higher, thus the offset in position) CMS Annual Review

  20. Chamber #1 CLCT 2,000 1,500 CLCT Rate (KHz) 1,000 data consistent with dead-time = 225 ns 500 0 0 500 1,000 1,500 2,000 2,500 3,000 Beam Intensity (KHz) Expected LCT rate at LHC < 25 KHz (ME1/1) CSC Trigger High Rate Tests CMS Annual Review

  21. CSC Track Finder Test Sector Processor 2 CSCs • Successfully passed optical link loopback tests and MPCSP chain tests using 40 MHz crystal oscillator to drive system • MPCSP optical link tests failed at the structured beam tests in May 2003 (link errors every few ms) • Clock was derived from TTC system (mivivxrx) • Combined clock jitter presumably too large to drive optical links • PLL was not used to clean clock (i.e. QPLL was not available) CMS Annual Review

  22. 2003 Unstructured Test Beam Results • Very high efficiencies achieved • Highest trigger efficiency of 99.9% required low rate (few kHz) • Improved DAQ throughput allowed readout up to 80k full events per spill. Typical “run” is 1 or 2 spills. • Improved scans taken: • Logic scope read out on most data • HV scan • Comparator threshold scan • Pattern requirements scan • Angle scans CMS Annual Review

  23. ALCT Production Testing - Example • ~510 Boards, ~200000 Channels • Semi-automated procedures • Using 3 test stations • 2 for testing • 1 for fixing • Crew of up to 14 students testing (3 FTE) • Sign-off sheets to track testing failures • Test before and after 2-day burn-in • 2 students trained for fixing • 1 engineer for difficult cases • 1 postdoc supervises it all CMS Annual Review

  24. Testing Other CSC Trigger Boards • TMBs (468+spares) testing (Emu): • Production testing with loop-back board tests all I/O (already built) • In-situ CMS testing by pulsing analog levels on CFEBs, reading comparators; also recording digital outputs to MPC and DDU. • MPCs (60+) production or in-situ CMS testing: • Inputs will be tested at full speed with FIFO on TMB • Outputs will be tested at full speed with input FIFO of SP • VME readout • SPs (12+): • Like MPC but with inputs from MPC, outputs to MS • CCBs (60+): • Simple module function, tested on bench and by exercising peripheral and Track Finder crate functions • MS (1+): • With only 1+spares, can be tested by hand as well as with input data from FIFOs on SP outputs CMS Annual Review

  25. Plans for Integration and Slice Tests • Test beam 2003 is the first full chain test from 2 CSC chambers to SP input • Sept. test beam cycle goals (see next slides): • Validate that correct trigger primitives are found and successfully received over optical links • Record as much data as possible under various detector configurations for future track identification studies • Will perform DTCSC TF interface tests the week following Sept. beam test • Next (6/04) structured test beam cycle will test pre-production boards (CCB, MPC, SP, TTC+QPLL) • 6/04-3/05 Slice Test (on surface) • Really begins with next summer test beam 6/04 • Use 2 full CSC peripheral crates, covering 2 stations x 60 degrees at SX5 • 9/1/05 Commissioning begins in UX5 • Integration with CMS-wide systems important for Track Finder: Slow controls (downloading), database, connection to Global Muon Trigger, software framework, time synchronization studies • 1/1/07 Commissioning ends at UX5 CMS Annual Review

  26. Sector Processor Clock Patch LVDS Repeater Delivers Multiplied Clock to Front FPGAs to Drive TLK2501 clock input VCXO and PLL added to clean synchronous clock • Voltage Controlled Crystal Oscillator PLL Patch • Low jitter Output • Cleans Backplane clock to drive SP logic • x2 BackPlane Clock supplies reference to TLK2501 CMS Annual Review

  27. SP Patch Results • Eagerly awaiting QPLL chips from CERN CMS Annual Review

  28. Preparation for Sept. 2003 Beam Test Cosmic ray test stand in Florida System brought to working order (everything now shipped to CERN) Scintillator Panels HV Supply CSCs TTCvx Periph Crate TF Crate MPC CCB SP TTCvi Dynatem TMB DDU CCB DMB SBS CMS Annual Review

  29. CSC Trigger FY02-05 L2,3 Milestones - I • Begin Proto. 2 • Begin MPC Proto. 2 • Begin SR/SP Proto. • Begin Backplane Proto. 2 • Begin CCC Proto. 3 • Begin Sorter Proto. • Finish Proto. 2 • Finish MPC Proto. 2 • Finish SR/SP Proto. • Finish Backplane Proto. 2 • Finish CCC Proto. 3 • Finish Sorter Proto. • Finish Proto. 2 Test • Finish MPC Proto. 2 Test • Finish SR/SP Proto. Test • Finish Backplane Proto. 2 Test • Finish CCC Proto. 3 Test • Finish Sorter Proto. Test • Finish Final Design • Finish MPC Final Design • Finish SR/SP Final Design • Finish Backplane Final Design • Finish CCC Final Design • Finish Sorter Final Design 5/14/01 10/1/01 10/1/01 10/1/01 10/1/01 5/14/01 6/24/03 9/30/02 1/30/03 2/28/03 8/19/02 3/31/03 9/30/03 4/30/03 4/30/03 4/30/03 4/30/03 9/30/03 3/31/04 3/31/04 3/31/04 3/31/04 3/31/04 3/31/04 √ √ √ √ √ √ √ √ √ (except PT memories, ordered) √ √ √ 2/28/04 9/30/03 1/30/04 2/28/04 √ but needs redesign 2/28/04 GMT integration? 7/30/04 3/31/04 7/30/04 7/30/04 7/30/04 7/30/04 CMS Annual Review

  30. CSC Trigger FY02-05 L2,3 Milestones - II • Begin Production • Begin MPC Production • Begin SR/SP Production • Begin Backplane Production • Begin CCC Production • Begin Sorter Production • Finish Production • Finish MPC Production • Finish SR/SP Production • Finish Backplane Production • Finish CCC Production • Finish Sorter Production • Begin Installation • Begin MPC Installation • Begin SR/SP Installation • Begin Backplane Installation • Begin CCC Installation • Begin Sorter Installation • Finish Installation • Finish MPC Installation • Finish SR/SP Installation • Finish Backplane Installation • Finish CCC Installation • Finish Sorter Installation 8/1/04 4/1/04 8/1/04 8/1/04 8/1/04 8/1/04 3/31/05 3/31/05 3/31/05 3/31/05 3/31/05 3/31/05 4/1/05 4/1/05 4/1/05 4/1/05 4/1/05 4/1/05 5/1/05 5/1/05 5/1/05 5/1/05 5/1/05 5/1/05 CMS Annual Review

  31. CSC Trigger FY02-05 L2,3 Milestones - III • Begin System Tests • Begin MPC System Tests • Begin SR/SP System Tests • Begin Backplane System Tests • Begin CCC System Tests • Begin Sorter System Tests • Finish System Tests • Finish MPC System Tests • Finish SR/SP System Tests • Finish Backplane System Tests • Finish CCC System Tests • Finish Sorter System Tests 6/1/05 6/1/05 6/1/05 6/1/05 6/1/05 6/1/05 9/30/05 9/30/05 9/30/05 9/30/05 9/30/05 9/30/05 CMS Annual Review

  32. Conclusions • The CSC system is in very good shape: • Chambers being mounted on disks at SX5 • Majority of the chambers already built and tested, including on-chamber electronics • Test beam showed that CSC peripheral crate electronics work very well under “battle conditions” • Of course, much work remains: • We especially need to validate the optical link clocking for MPC-SP data transfer • Production starts soon for peripheral crate electronics • Production planning will start soon for Track Finder (MPC, SP, MS) boards CMS Annual Review

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