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Introduction to VLSI Testing

Introduction to VLSI Testing. 李昆忠 Kuen-Jong Lee Dept. of Electrical Engineering National Cheng-Kung University Tainan, Taiwan. Problems to Think. How are you going to test A 32 bit adder A 32 bit counter A 32Mb cache memory A 10 7 -transistor CPU A 10 9 -transistor SOC. OUTLINE.

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Introduction to VLSI Testing

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  1. Introduction to VLSI Testing 李昆忠 Kuen-Jong Lee Dept. of Electrical Engineering National Cheng-Kung University Tainan, Taiwan

  2. Problems to Think • How are you going to test • A 32 bit adder • A 32 bit counter • A 32Mb cache memory • A 107-transistor CPU • A 109-transistor SOC

  3. OUTLINE • Introduction • Fault modeling • Fault simulation • Test generation • Automatic test pattern generation (ATPG) • Design for testability • Built-in self test • Synthesis for testability • An example

  4. Basic Concept of Testing Testing: To tell whether a circuit is good or bad VDD 0 0 0 0 0/1 0 Related fields Verification:To verify the correctness of a design Diagnosis:To tell the faulty site Reliability: To tell whether a good system will work correctly or not after some time. Debug: To find the faulty site and try to eliminate the fault

  5. Why Studying Testing? • Economics! • Reduce test cost (enhance profit) • Automatic test equipment (ATE) is extremely expensive • Shorten time-to-market • Market dominating or sharing • Guarantee IC quality and reliability Defects detected in Cost Rule of Ten: Cost to detect faulty IC increases by an order of magnitude Wafer 0.01 – 0.1 Packaged chip 0.1 – 1 Board 1 – 10 System 10 – 100 Field 100 – 1000

  6. Principle of Testing Input Patterns Output Response • Testing typically consists of • Applying set of test stimuli (input patterns, test vectors) to inputs of circuit under test (CUT), and • Analyzing output responses • The quality of the tested circuits will depend upon the thoroughness of the test vectors Circuit under Test (CUT) -1011 11-00 -0-1- 01--0 0-101 1-001 0011- -1101 1001- 01-11 Stored Correct Response Comparator Test Result

  7. Importance of testing N = # transistors in a chip p = prob. (a transistor is faulty) Pf = prob. (the chip is faulty) Pf = 1- (1- p) N If p = 10-6 N = 106 Pf = 63.2%

  8. Introduction • Integrated Circuits (ICs) have grown in size and complexity since the late 1950’s • Small Scale Integration (SSI) • Medium Scale Integration (MSI) • Large Scale Integration (LSI) • Very Large Scale Integration (VLSI) • Moore’s Law: scale of ICs doubles every 18 months • Growing size and complexity poses many and new testing challenges VLSI LSI M S I S S I

  9. Importance of Testing • Moore’s Law results from decreasing feature size (dimensions) • from 10s of m to 10s of nm for transistors and interconnecting wires • Operating frequencies have increased from 100KHz to several GHz • Decreasing feature size increases probability of defects during manufacturing process • A single faulty transistor or wire results in faulty IC • Testing required to guarantee fault-free products

  10. Vss Difficulties in Testing • Fault may occur anytime • - Design • - Process • - Package • - Field • Fault may occur at any place Vdd • VLSI circuit are large • - Most problems encountered in testing are NP-complete • I/O access is limited

  11. How to do testing From designer’s point of view: • Circuit modeling • Fault modeling • Logic simulation • Fault simulation • Test generation • Design for test • Built-in self test • Synthesis for testability Modeling ATPG Testable design

  12. Circuit Modeling • Functional model--- logic function • - f(x1,x2,...)=... • - Truth table • Behavioral model--- functional + timing • - f(x1,x2,...)=... , Delay = 10 • Structural model--- collection of interconnected components or elements A E B 1 0 G 1 C 0 D F 0

  13. VDD VDD VDD Levels of Structural Description • Switch level • Circuit level C C4 C1 B C3 C2 E • Gate level • Higher/ System level A E B G C D F

  14. A s-a-1 A s-a-0 B s-a-1 B s-a-0 C s-a-1 C s-a-0 D s-a-1 D s-a-0 E s-a-1 E s-a-0 F s-a-1 F s-a-0 G s-a-1 G s-a-0 14 faults Fault Modeling • The effects of physical defects • Most commonly used fault model: Single stuck-at fault E A B G C D F • Other fault models: • - Break faults, Bridging faults, Transistor stuck-open faults, • Transistor stuck-on faults, Delay faults

  15. # faults detected FC = # faults in fault list Test faults detected FC Fault Coverage (FC) Example: 6 stuck-at faults ( a0,a1,b0,b1,c0,c1 ) 1 1 1 1 0 0 0 0 0 c a b c1 a1,c1 a0,b0,c0 a0,b0,c0,c1 all {(0,0)} {(0,1)} {(1,1)} {(0,0),(1,1)} {(1,0),(0,1),(1,1)} 16.67% 33.33% 50.00% 66.67% 100.00%

  16. Wafer Yield (Chip Yield, Yield) Good Chip Faulty Chip Defects Wafer Wafer yield = 12/22 = 0.55 Wafer yield = 17/22 = 0.77

  17. Shipped Parts IC Fabrication Testing Quality: Defective parts per million (DPM) Yield: Fraction of good parts Rejects Testing and Quality • Quality of shipped parts is a function of yield Y and the test (fault) coverage T • Defect level (DL, reject rate in textbook): fraction of shipped parts that are defective

  18. Yield (Y) Fault Coverage (T) 50% 90% 67,000 75% 90% 28,000 90% 90% 10,000 95% 90% 5,000 99% 90% 1,000 90% 90% 90% 95% 90% 99% 90% 99.9% Defect Level, Yield & Fault Coverage DL: defect level Y: yield T: fault coverage ～ DL = 1 - Y (1-T) DPM (DL) 10,000 5,000 1,000 100

  19. Logic simulation • To determine how a good circuit should work • Given input vectors, determine the normal • circuit response A I C B C A D CC2 CC1 IR G B F B RB IF F E CDE CJE C E H D E

  20. E s.a.0 1/0 1 1 1/0 Fault simulation • To determine the behavior of faulty circuits 1 A 0 B G 0 F C 1 0 D • Given a test vector, determine all faults that • are detected by this test vector. Example: Test vector (1 1) detects { a0, b0, c1} 1 A 0 C B 1

  21. Test generation • Given a fault, identify a test to detect this fault Example: 1 1/0 0 A D 1 1/0 B F 1 C E 0 To detect D s-a-0, D must be set to 1. Thus A=B=1. To propagate fault effect to the primary output E must be 1. Thus C must be 0. Test vector: A=1, B=1, C=0

  22. Automatic Test Pattern Generation • ATPG: Given a circuit, identify a set of test vectors to detect all faults under consideration. Input circuit Form fault list More faults? No Exit Yes Select a fault Fault dropping Test generation Fault simulation

  23. Cannot detect the fault 1 Fault detected 1 Difficulties in Test Generation 1. Reconvergent fanout 0/1 A 0 s-a-1 D 1 0 F B 0/1 1 C E 0

  24. Difficulties in Test Generation (cont.) 2. Sequential test generation PIs POs Combinational part Y J K clk Y CK

  25. Testable Design • Design for testability (DFT) • •ad hoc techniques • Scan design • Boundary Scan • Built-In Self Test (BIST) • Random number generator (RNG) • Signature Analyzer (SA) • Synthesis for Testability

  26. MUX Example of ad hoc Techniques Insert test points T/N

  27. Scan Design Original design Modified design Combinational logic Combinational logic PIs POs PIs POs SO SFF FF SFF FF SFF FF T/N SI

  28. Q,SO DI Q D Q D MUX SI CK CK N/T (SE) Scan Cell Design Q DI Q,SO Q DI DI F F SI F FT F + FT Most cell libraries now have scan cells!

  29. Q D Q D SI SI Scan Register Combinational Circuits Q D Q D SI SI SO SE CLK

  30. Boundary Scan I/O Pad Boundary scan cell Boundary scan path TRST* TDI APPLICATION LOGIC Sout Misc. registers TMS Instruction register T A P BIST register TCK Bypass register Scan register M U X Sin TDO TRST*:Test rest (Optional) TDI: Test data input TD0: Test data output TCK: Test clock TMS: Test mode select

  31. Boundary Scan (Cont.) TRST* TRST* Sout Sout APPLICATION LOGIC APPLICATION LOGIC TDI TDI Misc. registers Misc. registers TMS TMS Instruction register Instruction register T A P T A P BIST register BIST register Bypass register Bypass register TCK TCK Scan register Scan register Sin Sin M U X M U X TDO TDO TRST* TRST* Sout Sout APPLICATION LOGIC APPLICATION LOGIC TDI TDI Misc. registers Misc. registers TMS TMS Instruction register Instruction register T A P T A P BIST register BIST register Bypass register Bypass register TCK TCK Scan register Scan register Sin M U X Sin M U X TDO TDO

  32. Built-In-Self Test (BIST) • Places the job of device testing inside the device itself • Generates its own stimulus and analyzes its own response from system to system circuit under test mux Response Analyzer pattern generator BIST Controller good/fail bistdone biston

  33. F/F Built-In-Self Test (BIST)(Cont.) • Two major tasks • - Test pattern generation • - Test result compaction • Usually implemented by linear feedback • shift register F/F F/F

  34. F/F F/F F/F F/F Random Number Generator (RNG) 0001 1000 0100 0010 1001 1100 0110 1011 0101 1010 1101 1110 1111 0111 0011 0001 (repeat) · · · · 1. Generate “pseudo” random patterns 2. Period is 2n - 1

  35. + + + Signature Analyzer (SA) Input sequence 10101111 (8 bits) 4 1 2 3 5 Z Time Input stream Register contents Output stream 0 1 . . 5 6 7 8 1 0 1 0 1 1 1 1 0 0 0 0 0 Initial state 1 0 1 0 1 1 1 1 0 0 0 0 . . . . 1 0 1 0 1 1 1 1 1 0 0 0 0 1 0 1 1 0 0 0 0 1 0 1 0 0 1 0 1 1 0 1 Quotient Remainder

  36. Signature Analyzer (SA) (cont.) • A LFSR performs polynomial division • Probability of aliasing error = 1/2n (n: # of FFs)

  37. Memory BIST Architecture Before After sys_di Memory Module Memory Module data sys_addr di sys_wen clk q hold_l data addr rst_l test_h si wen so se

  38. clk rst si se Memory BIST Architecture (Cont.) sys_addr di Memory Module sys_di data addr wen sys_wen Algorithm-Based Pattern Generator rst_l clk q compress_h hold_l Compressor test_h so BIST Circuitry

  39. MUX CPU Test Control Architecture Scan_i Scan_o Scan path Scan_en logic rst_l clk Bist control Memory hold_l test_h bist_se bist_so TDO compressor bist decoder int_scan mbist scan decoder bist_si decoder TDI IR TCK TAP Controller TMS

  40. Problems re-thinking • A 32-bit adder --- ATPG • A 32-bit counter --- Design for testability + ATPG • A 32MB Cache memory --- BIST • A 107-transistor CPU --- All test techniques • An SOC

  41. Conclusions • Testing is becoming a major factor in design optimization • Conventionally, the designer often optimize one of the three attributes: speed, area, and power. • At present, a fourth attribute is considered: Testability. • Two major fields in testing • ATPG --- Fault simulation --- Test generation • Testable design --- Design for testability --- Built-in self-test --- Synthesis for testability

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