Power Reduction Techniques in Decimation Filter

1. Power Reduction TechniquesinDecimation Filter Seyyedeh Maryam Mortazavi Zanjani

2. Outline • Introduction to Decimation Filter. • Non-recursive Sinc Filter. • CIC Filter with Low Power Implementation Technique. • Sinc Filter Based on the Direct Implementation of the Convolution Relationship. 2

3. Analog to Digital ΣΔ Converter Figure 1: Block diagram of ΣΔ analog to digital converter. Basic concept: Exchange resolution in time for that in amplitude through the use of oversampling, feedback and digital filtering. 3

4. ΣΔ Data Converter [1] The digital decimation filter must suppress out-of-band noise. Figure 2: ΣΔ analog to digital converter. 4

5. Decimation Filter [1] Decimation filtering is commonly accomplished using FIR, rather than IIR, filters. FIR filters have a linear phase response, which can be of considerable importance in some applications. • Single stage decimation filter. • If a single FIR stage is used for decimation, the number of coefficients needed may be too high e.g. 17,500 for a practical, power-efficient implementation. • Multistage decimation filter. 5

6. Multi-Stage Decimation Filter By decimating in multiple stages, the complexity of the whole filter is reduced, and the subsequent filters operate at lower sampling rate, further reducing the power consumption. • Sinc Filter. • Droop correction filter. • FIR filter such as half-band filter. 6

7. First Stage of Decimation [1] A convenient means of placing zeros at multiples of fD is to use “sinc filter”, with the transfer function. Figure 3: Sinc filter. 7

8. First Stage of Decimation Figure 4: Sinc filter. 8

9. Benefits & Drawbacks of Sinc Filter [2] • Benefits of sinc filter • No multiplier • Regular structure • Wide range of rate change • Drawbacks of sinc filter • In-band droop. • Insufficient attenuation in stop-band. 9

10. First Stage of Decimation [1] • In order to avoid a significant increase in base-band quantization noise upon re-sampling, a cascade of Sinc filters is typically used to provide sufficient attenuation near multiples of fD. • The cascade of sinc filters results in a significant amount of in-band droop, which must be compensated for in the final stages of decimation. 10

11. Cascade of K Sinc Filters [1] Figure 5: Magnitude response of cascaded sinc filters. 11

12. Cascaded Integrator-Comb (CIC) Structure [3] Figure 6: (a) Direct implementation of CIC filter. (b) CIC filter implementation with numerator section after the resampling operation. 12

13. CIC Structure [4] In [4], it is shown that if 2’s complement wrap-around arithmetic is used, the overflow problem can be avoided as long as the register width is greater than or equal to the value given by the following equation: Output No. of Bits = Input No. of Bits + K×log2(M) Figure 7: Implementation of second order CIC filter. 13

14. Non-recursive Sinc Filter [2] Figure 8: Implementation of third order non-recursive Sinc filter. 14

15. CIC Filter with Low Power Implementation Techniques [5] Figure 10: The non-recursive architecture for comb decimation filters. Figure. 11: An implementation of stage i by cascading (1 + z-1) computational elements. 15

16. Comparison of CIC & Non-recursive Sinc Filters [2] • Cascaded integrator comb • Higher power consumption since the integrator stage works at the highest over-sampling rate with a large internal word length. • The circuit speed will be limited by the large word length and recursive loop of the integrator stage. • Non-recursive Sinc Filter • Lower power consumption since the sampling rate reduces through each stage by a factor of 2 and the first few stages have shorter word length. • Circuit can reach higher speed because in the non-recursive algorithm its first stage always has smaller word length compared with the integrator stage in the recursive algorithm. 16

17. Comparison of CIC & Non-recursive Sinc Filters [2] Figure 9: Comparisons of the recursive and the non-recursive algorithm when m=1 and k=5: (a) Estimated core power consumption vs. decimation ratio when fs = 70MHz: (b) Estimated highest working frequency vs. decimation ratio. (c) Estimated size vs. decimation ratio. 17

18. CIC Filter with Low Power Implementation Techniques [5] Figure 10: The non-recursive architecture for comb decimation filters. Figure. 11: An implementation of stage i by cascading (1 + z-1) computational elements. 18

19. CIC Filter with Low Power Implementation Techniques [5] Figure 12: Block diagram of fifth order non-recursive Sinc filter. 19

20. CIC Filter with Low Power Implementation Techniques [5] Figure 13: Implementation of E0(z) (a) The direct-form structure for FIR filter; (b) The data-broadcast structure; (c) The multiplications are simplified to a few of shifts and adds; (d) The low-power implementation with substructure sharing. 20

21. CIC Filter with Low Power Implementation Techniques [5] Figure 14: The block diagram of the fifth order comb decimation filter. 21

22. CIC Filter with Low Power Implementation Techniques [5] Figure 15: Low power implementation of 5x(= 22x + 20x). 22

23. Sinc Filter Based on the Direct Implementation of the Convolution Relationship [6] Figure 16: Implementation of x(0)+4x(-1)+10x(-2). 23

24. Sinc Filter Based on the Direct Implementation of the Convolution Relationship [6] 24

25. Sinc Filter Based on the Direct Implementation of the Convolution Relationship [6] Figure 17: Implementation of the whole sinc4 filter. 25

26. Sinc Filter Based on the Direct Implementation of the Convolution Relationship [6] • The circuit of Fig. 17 requires a total of 65 1-bit memory cells, 5 binary adders from 4 to 8 bits and three logic gates. • A standard implementation based on the CIC architecture requires at least 8 register and 8 adders or subtractors, each handling a number of bits boutequal to bout = 1 + 4 log24 = 9 • Therefore the proposed architecture reduces the hardware complexity. Furthermore the integrators in the CIC approach run at the incoming rate of 8KHz, while, as mentioned before, all the blocks in the proposed architecture run at 2KHz directly. 26

27. Comparison of Power

28. Summary and Conclusion In addition to suppressing quantization noise, the decimation filter must attenuate out-of- band signals and noise components that are aliased into the base-band upon re-sampling. A number of techniques has been introduced to reduce power consumption in decimation filter. As Sinc filter works at the highest frequency, it consumes most of power, consequently these techniques try to save power in sinc filter. 28

29. References • Bruce A. Wooley, “VLSI data conversion circuits handouts,” Department of Electrical Engineering Stanford University, Spring 2001-2002. • Y. Gao, L. Jia, J. Isoaho and H. Tenhunen, “A comparison design of comb decimators for sigma-delta analog-to-digital converters,” Analog Integrated Circuits and Signal Processing, vol. 22, pp. 51-60, 1999. • Carol J. Barrett, “Low-Power Decimation Filter Design for Multi-Standard Transceiver Applications,” Master of Science in Electrical Engineering University of California, Berkeley, 1998. • Eugene Hogenauer, “An Economical Class of Digital Filters for Decimation and Interpolation,” IEEE Trans. on Acoustics, Speech, and Signal Processing, Vol. ASSP-29, No. 2, April 1981. • Yonghong Gao, Lihong Jia, and Hannu Tenhunen, "A fifth-order COMB decimation filter for multi-standard transceiver applications,"inIEEE Proc. ISCAS’00, May 28-31, Geneva, Switzerland, pp. 89-92. • Andrea Gerosa, Andrea Neviani, “A Low-power decimation filter for a sigma-delta converter based on a power-optimized sinc filter,” converters,'' in IEEE Proc. ISCAS‘04, pp. 245-248, 2004. 29