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Digital Electronics and Computer Interfacing

Digital Electronics and Computer Interfacing. Tim Mewes 3. Digital Electronics. 3.7 Flip-flops . A flip-flop is a digital circuit that is capable of serving as a one bit memory A flip-flop is constructed using gates.

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Digital Electronics and Computer Interfacing

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  1. Digital Electronics and Computer Interfacing Tim Mewes 3. Digital Electronics

  2. 3.7 Flip-flops • A flip-flop is a digital circuit that is capable of serving as a one bit memory • A flip-flop is constructed using gates • But we said that the output of a gate only depends on its inputs and not on its history?! No memory – output remains only as long as the inputs are set 0 1 1 • So how could it possibly work? • Somehow create a “loop” – called Feedback Digital Electronics and Computer Interfacing

  3. S Q Q R 3.7.1 Set/reset flip-flop (SR flip-flop) • One possible implementation: NAND gate latch Digital Electronics and Computer Interfacing

  4. Q 3.7.1 Set/reset flip-flop (SR flip-flop) • Reset of the flip-flop: S=1, R=0 S 1 Q 0 0 ? 1 1 R 0 Digital Electronics and Computer Interfacing

  5. Q 3.7.1 Set/reset flip-flop (SR flip-flop) • Set of the flip-flop: S=0, R=1 S 0 Q 1 1 ? 0 0 R 1 Digital Electronics and Computer Interfacing

  6. Q 3.7.1 Set/reset flip-flop (SR flip-flop) • What happens when we now change to: S=1, R=1 ? S 1 0 Q 1 0 1 0 R 1  Flip-flop does not change its output ! (latch) Digital Electronics and Computer Interfacing

  7. Q  NOT(Q) !!! Q 3.7.1 Set/reset flip-flop (SR flip-flop) • What happens for: S=0, R=0 ? S 0 Q 1 ? Invalid state! ? 1 R 0 • Both outputs are 1! Digital Electronics and Computer Interfacing

  8. S Q Q R 1 S 0 1 R 0 1 Q 0 3.7.1 Set/reset flip-flop (SR flip-flop) • Summary invalid Timing diagram Digital Electronics and Computer Interfacing

  9. S’ Q E Q R’ 3.7.2 Gated SR flip-flop • Sometimes also called: Clocked SR flip-flop The input E is called enable input or clock input Digital Electronics and Computer Interfacing

  10. Q Thus: Q=0 and Q=1 3.7.2 Gated SR flip-flop • Reset of the gated SR flip-flop: S’=0, R’=1 and E=1 S’ S 0 1 Q 0 E 1 1 1 0 R’ R 1 This corresponds to the Reset case (S=1, R=0) of the SR flip-flop (page 4) Digital Electronics and Computer Interfacing

  11. Q Thus: Q=1 and Q=0 3.7.2 Gated SR flip-flop • Set of the gated SR flip-flop: S’=1, R’=0 and E=1 S’ S 1 0 Q 1 E 1 1 0 1 R’ R 0 This corresponds to the Set case (S=0, R=1) of the SR flip-flop (page 5) Digital Electronics and Computer Interfacing

  12. Q 3.7.2 Gated SR flip-flop • What happens if we now set E=0? S’ S 0 1 1 Q 1 0 E 0 0 1 0 1 R’ R 0 1 With E=0 the flip-flop does not change its outputs! Digital Electronics and Computer Interfacing

  13. S’ Q E Q R’ Q 3.7.2 Gated SR flip-flop • Summary invalid 1 E 0 1 S’ 0 1 R’ 0 1 0 Timing diagram Digital Electronics and Computer Interfacing

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