1. Status of NA62 straw readout

2. SRB • Final design stage • Drawing schematics • Optimizing FPGA pinout • Changes in connectivity and data flow • Embedded CPU removed • Not enough connectivity • Extra chip would be complicated in given time schedule • Added high speed SRAM (10ns) for histograms • Pipelined access 2-3 clock cycles (read – modify – write) • Delay of every cover clock line (16 lines) must be adjustable and clock synchronized to TTC • Trying 2 solutions • Use FPGA feature • Jitter too big • test of special chips • Si5338 – ‘zero’ delay feature, up to 40ns output delay for every line

3. 4x XTAL 25 MHz 50 MHz Si5338 Si5338 D E T E C T O R 125 MHz 40.07658 MHz Si5338 BUFFER With AUTO SWITCH Si53302 TTC TTCRX Si5338 Si5338 Si5338

4. SRB – components L0 PROCESSOR L0 LOOK_UP TABLE L0 OUT VME INTF ON-LINE MONITOR LEMO TTC TTCRx COVERS TIME REMAP WORK DATA TO PC FARM COVER CONTROL, DATA, SYNCH EVENT PROCESSOR 2(4)GB DDR3

5. Definition of data formats version all data (without L0) • Full data for 1 straw 48 bits • 32 bits coarse time • 16 MSB coarse time send as a UDP first word followed by number of 32bit data until end of UDP packet • If still more data • Restart UDP packet with the same 16bit coarse time • If 16bit coarse time changes • Finish UDP packet and start new one • 16 LSB coarse time correspond to 1.6ms • With data rate 250straw*2*60kHz*1.3*32bits = 1.25Gb/s this corresponds to ~250kB of data per 1 16bit time slot

6. Definition of data formats version 2 (with L0)

7. SRB • Plans • Schematics still ~2 weeks • Also depends on CAE • Test data format compliance with ALTERA demonstrator board • Prototype May/June • Test with TDAQ in August