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Hardware status GOLD

Hardware status GOLD. Update 03 Mar. 2010. GOLD floor plan (approximate). Z3. L. 5 * XC6VLX ( L,M ) 4* XC6VHX ( H ) 144 multigigabit links in zone 2 (equiv. 22300 bit / BC). L. Opto. L. L. M. Z2. H. H. 890Gb/s total. H. H. Z1. GOLD – current status.

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Hardware status GOLD

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  1. Hardware status GOLD Update 03 Mar. 2010

  2. GOLD floor plan(approximate) • Z3 • L • 5 * XC6VLX (L,M) • 4* XC6VHX (H) • 144 multigigabit links in zone 2 (equiv. 22300 bit / BC) • L • Opto • L • L • M • Z2 • H • H • 890Gb/s • total • H • H • Z1

  3. GOLD – current status • Schematics partially done • Routing as shown: • xGb/s links hand routed  • ‘Low’ speed links (1Gb/s) to be auto routed

  4. GOLD status • Schematics and layout under way • Components ordered. Lead time: • AVAGO (2*T, 2*R) : arrived • SNAP12 : mid April • Xilinx XCVLXT: 8-10 weeks • Production of Xilinx HXT devices delayed Firmware activities: Currently working on extension of VME bus from 9U processor crates, via BLT module, optically into GOLD

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