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332:479 Concepts in VLSI Design Lecture 8 DC & Transient Response

332:479 Concepts in VLSI Design Lecture 8 DC & Transient Response. David Harris and Michael Bushnell Harvey Mudd College and Rutgers University Spring 2004. Outline. DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Inverter Voltage Transfer Characteristics

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332:479 Concepts in VLSI Design Lecture 8 DC & Transient Response

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  1. 332:479 Concepts in VLSIDesignLecture 8 DC & Transient Response David Harris and Michael Bushnell Harvey Mudd College and Rutgers University Spring 2004

  2. Outline • DC Response • Logic Levels and Noise Margins • Transient Response • Delay Estimation • Inverter Voltage Transfer Characteristics • Static Load and Pseudo-nMOS Devices • Transmission Gates and Tri-state Inverter • Summary Concepts in VLSI Des. Lec. 8

  3. Activity 1)If the width of a transistor increases, the current will  increase decrease not change 2)If the length of a transistor increases, the current will increase decrease not change 3)If the supply voltage of a chip increases, the maximum transistor current will increase decrease not change 4)If the width of a transistor increases, its gate capacitance will increase decrease not change 5)If the length of a transistor increases, its gate capacitance will increase decrease not change 6)If the supply voltage of a chip increases, the gate capacitance of each transistor will increase decrease not change Concepts in VLSI Des. Lec. 8

  4. Activity 1)If the width of a transistor increases, the current will  increase decrease not change 2)If the length of a transistor increases, the current will increase decrease not change 3)If the supply voltage of a chip increases, the maximum transistor current will increase decrease not change 4)If the width of a transistor increases, its gate capacitance will increase decrease not change 5)If the length of a transistor increases, its gate capacitance will increase decrease not change 6)If the supply voltage of a chip increases, the gate capacitance of each transistor will increase decrease not change Concepts in VLSI Des. Lec. 8

  5. DC Response • DC Response: Vout vs. Vin for a gate • Ex: Inverter • When Vin = 0 -> Vout = VDD • When Vin = VDD -> Vout = 0 • In between, Vout depends on transistor size and current • By KCL, must settle such that Idsn = |Idsp| • We could solve equations • But graphical solution gives more insight Concepts in VLSI Des. Lec. 8

  6. Transistor Operation • Current depends on region of transistor behavior • For what Vin and Vout are nMOS and pMOS in • Cutoff? • Linear? • Saturation? Concepts in VLSI Des. Lec. 8

  7. nMOS Operation Concepts in VLSI Des. Lec. 8

  8. nMOS Operation Concepts in VLSI Des. Lec. 8

  9. nMOS Operation Vgsn = Vin Vdsn = Vout Concepts in VLSI Des. Lec. 8

  10. nMOS Operation Vgsn = Vin Vdsn = Vout Concepts in VLSI Des. Lec. 8

  11. pMOS Operation Concepts in VLSI Des. Lec. 8

  12. pMOS Operation Concepts in VLSI Des. Lec. 8

  13. pMOS Operation Vgsp = Vin - VDD Vdsp = Vout - VDD Vtp < 0 Concepts in VLSI Des. Lec. 8

  14. pMOS Operation Vgsp = Vin - VDD Vdsp = Vout - VDD Vtp < 0 Concepts in VLSI Des. Lec. 8

  15. CMOS Inverter Switching • Procedure to graphically get transfer characteristic: • Reflect p device characteristic about x-axis • Take absolute value of p device characteristic • Superimpose 2 characteristics • Solve for common points of Vgs intersection • Vinn = Vinp, Idsn = Idsp • Switching point = VDD / 2 Concepts in VLSI Des. Lec. 8

  16. I-V Characteristics • Make pMOS is wider than nMOS such that bn = bp Concepts in VLSI Des. Lec. 8

  17. Current vs. Vout, Vin Concepts in VLSI Des. Lec. 8

  18. Load Line Analysis • For a given Vin: • Plot Idsn, Idsp vs. Vout • Vout must be where |currents| are equal in Concepts in VLSI Des. Lec. 8

  19. Load Line Analysis • Vin = 0 Concepts in VLSI Des. Lec. 8

  20. Load Line Analysis • Vin = 0.2VDD Concepts in VLSI Des. Lec. 8

  21. Load Line Analysis • Vin = 0.4VDD Concepts in VLSI Des. Lec. 8

  22. Load Line Analysis • Vin = 0.6VDD Concepts in VLSI Des. Lec. 8

  23. Load Line Analysis • Vin = 0.8VDD Concepts in VLSI Des. Lec. 8

  24. Load Line Analysis • Vin = VDD Concepts in VLSI Des. Lec. 8

  25. Load Line Summary Concepts in VLSI Des. Lec. 8

  26. DC Transfer Curve • Transcribe points onto Vin vs. Vout plot Concepts in VLSI Des. Lec. 8

  27. Operating Regions • Revisit transistor operating regions Concepts in VLSI Des. Lec. 8

  28. Operating Regions • Revisit transistor operating regions Concepts in VLSI Des. Lec. 8

  29. Five Regions of Operation • Transition – both transistors on – short current pulse drawn from supply • A 0 Vin Vtn, n cutoff, p linear, Vout = VDD • B Vtn Vin < VDD / 2, p linear, n saturated • For n, Vgs = Vin • Idsn = bn [ Vin – Vtn ]2 2 • For p, Vgs = Vin – VDD; Vds = (Vout - VDD) • Idsp = - bp (Vin – VDD – Vtp) (Vout – VDD) – (Vout – VDD)2 2 ] [ Concepts in VLSI Des. Lec. 8

  30. Regions of Operation • Let Idsp = - Idsn, and then • Vout = (Vin–Vtp) + (Vin–Vtp)2 – 2(Vin- - Vtp) VDD – bn (Vin– Vtn)2 • bp • C Both n and p devices saturated – unstable • 2 current sources in series • Idsp= - ½ bp (Vin – VDD – Vtp)2 • Idsn = ½ bn (Vin - Vtn)2 VDD 2 Concepts in VLSI Des. Lec. 8

  31. Regions of Operation • WithIdsp = - Idsn, • Vin = VDD + Vtp + Vtn • 1 + • If bn = bp and Vtn = - Vtp, you get: Vin = VDD/2 • Can have Vin – Vtn < Vout < Vin – Vtp when Vin = VDD/2 • Non-ideal current source behavior: • Slight slope due to channel length modulation bn bp bn bp Concepts in VLSI Des. Lec. 8

  32. Inverter Behavior • Very steep transition between logic 1 and 0 • Highly desirable • Small Vinchange causes big Vout change • Much better than nMOS inverter • Logic gate threshold Vinv – point where Vin = Vout Concepts in VLSI Des. Lec. 8

  33. Regions of Operation • Dp in saturation, n in linear region • VDD/2 < VinVDD + Vtp • Idsp = - ½ bp (Vin – VDD – Vtp)2 • Idsn = bn [ (Vin – Vtn) Vout - ½ Vout2 ] • With Idsp = - Idsn, then • Vout = (Vin – Vtn) - (Vin – Vtn)2 - (Vin – VDD –Vtp)2 bp bn Concepts in VLSI Des. Lec. 8

  34. Regions of Operation • E Vin > VDD + Vtp, p device cut-off, n linear • Vgsp = Vin – VDD, greater than Vtp so Vout = 0 Concepts in VLSI Des. Lec. 8

  35. Beta Ratio • If bp / bn 1, switching point will move from VDD/2 • Called skewed gate • Other gates: collapse into equivalent inverter Concepts in VLSI Des. Lec. 8

  36. Beta Ratio Influence on Transfer Characteristic • baT-1.5IdsaT-1.5 • Due to decreased m as T increases • Gate threshold Vinv – state where Vin = Vout • To change , must change channel L or W • = 1 is nice – a capacitive load can charge & discharge in equal times • Equal current source & sink capabilities bn bp bn bp Concepts in VLSI Des. Lec. 8

  37. Temperature Dependency bn bp • Since voltage transfer depends on • So, it is roughly independent of T • Vtn, Vtp decrease slightly as T increases: • Extent of Region A reduced • Extent of Region E increased • If T rises by 50 oC, Vtn & Vtp each drop 200 mV • 0.2 V shift in inverter threshold Concepts in VLSI Des. Lec. 8

  38. Noise Margins • How much noise can a gate input see before it does not recognize the input? Concepts in VLSI Des. Lec. 8

  39. Logic Levels • To maximize noise margins, select logic levels at Concepts in VLSI Des. Lec. 8

  40. Logic Levels • To maximize noise margins, select logic levels at • Unity gain point of DC transfer characteristic Concepts in VLSI Des. Lec. 8

  41. Noise Margins • Desirable to have VIH = VIL and at a value midway on logic swing from VOL to VOH • Prefer to haveNMH = NML,but sometimes we compromise this for speed Concepts in VLSI Des. Lec. 8

  42. Transient Response • DC analysis tells us Vout if Vin is constant • Transient analysis tells us Vout(t) if Vin(t) changes • Requires solving differential equations • Input is usually considered to be a step or ramp • From 0 to VDD or vice versa Concepts in VLSI Des. Lec. 8

  43. Inverter Step Response • Ex: find step response of inverter driving load cap Concepts in VLSI Des. Lec. 8

  44. Inverter Step Response • Ex: find step response of inverter driving load cap Concepts in VLSI Des. Lec. 8

  45. Inverter Step Response • Ex: find step response of inverter driving load cap Concepts in VLSI Des. Lec. 8

  46. Inverter Step Response • Ex: find step response of inverter driving load cap Concepts in VLSI Des. Lec. 8

  47. Inverter Step Response • Ex: find step response of inverter driving load cap Concepts in VLSI Des. Lec. 8

  48. Inverter Step Response • Ex: find step response of inverter driving load cap Concepts in VLSI Des. Lec. 8

  49. Delay Definitions • tpdr: • tpdf: • tpd: • tr: • tf: fall time Concepts in VLSI Des. Lec. 8

  50. Delay Definitions • tpdr: rising propagation delay • From input to rising output crossing VDD/2 • tpdf: falling propagation delay • From input to falling output crossing VDD/2 • tpd: average propagation delay • tpd = (tpdr + tpdf)/2 • tr: rise time • From output crossing 0.2 VDD to 0.8 VDD • tf: fall time • From output crossing 0.8 VDD to 0.2 VDD Concepts in VLSI Des. Lec. 8

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