1. Altera Techmapper Peter Lieber Adam Arnesen

2. Altera Techmapper • Integrate an Altera tech mapper into JHDL • We must reverse engineer JHDL • We must find the best primitives to use • Where do we jump into the Altera tools? • Motivation • Altera has a nice scan chain built in. • Can we use it?

3. Goals • Understand how to add a tech mapper to the JHDL toolset. • Implement a simple, generic Altera FPGA tech mapper with support for Cyclone and Stratix Devices • Time permitting, implement an extension to JHDL that will insert a scan chain into existing designs.

4. Scope • We will only implement about level 1.5 of JHDL for the mapper. • Gates: inv, and, or, xor (LPM) • Other: dff, inbuffer, outbuffer (Generic Altera) • We will not implement hardware mode • The scan chain is a step in that direction, but as far as we go.

5. Scan Chain • Altera Scan Chain

6. Primitives

7. Altera Tools

8. Altera Tools • No entry after synthesis tool • Altera likes to reserve the right to re-synthesize your design if it doesn’t like what you’ve done. • Only CPLDs support EDIF netlist input • We must either use VQM, which is mapped verilog, or use structural HDL. • We will use structural HDL because there is a VHDL netlister in JHDL.

9. Schedule • Week 1: Understanding of tech mapper and interface into JHDL • Week 2: Basic tech mapper implemented • Week 3: Integration and Scan Chain • Extra: Get JHDL working with Eclipse

10. Review • What are we going to do? • Implement an Altera Techmapper • What are we intending to accomplish? • Successfully integrate a new techmapper into JHDL • Implement automatic scan chain insertion • What are we NOT going to do? • Implement hardware mode • Techmapper will only by level 1.5 • Schedule • Techmapper interface -> Techmapper -> Scan Chain