1 / 12

Introduction to MODIP Design Flow: Verification, Integration, and Synthesis

This presentation by Joaquin Canovas provides a comprehensive overview of the MODIP design flow, covering crucial processes such as requirements gathering, verification methodologies, integration techniques, and backend software development. With a focus on design compliance and physical implementation, it emphasizes the importance of early verification to reduce the cost of fixing bugs. Key topics include block verification, synthesis from RTL to gates, and system simulations, ensuring a thorough understanding for engineers involved in hardware design projects.

tim
Télécharger la présentation

Introduction to MODIP Design Flow: Verification, Integration, and Synthesis

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. MODIP: Design flow Introduction Joaquin Canovas

  2. Outline • About myself • PROCESS OVERVIEW • VERIFICATION • INTEGRATION • SYNTHESIS • BACKEND SOFTWARE • WORKING ENVIRONMENT

  3. About myself

  4. Process overview • Requirements, customers/Standard/… (PM, SM, SA) • FSMs + Datapaths + ALUs + Memories + … = Block • Block Verification = Is the design compliant with the specs? • Block1+Block2+…+BlockN = Subsystem / Integration • Integration correct? +Additional tests at sybsystem. • Physical implementation.

  5. verification • Verification, why? - The cost of fixing a bug grows exponentially with the stage at which it is detected/fixed • Examples: • Block Verification: • Statement of compliance/implementation • Subsystem Verification: • Connections, data transfers, interfaces, address mapping… • DFT: • Can the manufactured silicon be tested? • Static Timing Analysis: • Delay calculations/simulations. Circuit frequency limitation. • Electrical verification…

  6. INTEGRATION • Block Diagram:

  7. Synthesis • RTL (HDL) 2 GATES (Verilog): • Synthesis: • RTL, Verilog, SystemC,… NETLIST • Design “description” Design Implementation • Floorplan layout: Placing the design and routing.

  8. BACKEND • FLOORPLAN LAYOUT (BE): • Placing the design and routing. • Real design: • Block diagram:

  9. Software • Examples: • SYSTEM SIMULATION: • Algorithm development/simulation, bit widths, performance,… • VERIFICATION PLATFORMS: • Need to start SW development as soon as possible • Radio Access Technology (RAT) SW: • Network Signaling (NSSW)

  10. Working environment SA PM & SM  Requirements  Design  Verification  Phys. Implementation  Project Office HW DESIGN BLOCK VER INTEG. SS. VER RTL2GATES BE

  11. QueStions?

More Related