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EXTERNAL INTERRUPT REQUEST MODULE (IRQ) PowerPoint Presentation
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EXTERNAL INTERRUPT REQUEST MODULE (IRQ)

EXTERNAL INTERRUPT REQUEST MODULE (IRQ)

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EXTERNAL INTERRUPT REQUEST MODULE (IRQ)

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  1. EXTERNAL INTERRUPT REQUEST MODULE (IRQ)

  2. Module Objective • By the end of this module, you should be able to: • Enable/disable IRQ interrupts • Configure the trigger sensitivity • Acknowledge the interrupts • Configure port external interrupts

  3. IRQ LVI Direct Memory Access Module (DMA) System Integration Module (SIM) Clock Generation Module (CGM) Timer Interface Module (TIM) 68HC08 CPU RESET COP BREAK Internal Bus (IBUS) Random Access Memory (RAM) Serial Peripheral Interface (SPI) Electronically Programmable Memory (EPROM) Monitor ROM Serial Communications Interface (SCI) EXTERNAL INTERRUPT (IRQ) MODULE • Supports external interrupt functions • Two dedicated external interrupt pins • IRQ1/Vpp and IRQ2 • Individually programmable • Separate interrupt masks • IRQ2 Interrupt Disable • Configurable Port as external interrupts • Allows additional external interrupts

  4. READ: V 1 1 H I N C Z CCR WRITE: RESET: x 1 1 x 1 x x x Global Interrupt Mask • Code Condition Register (CCR) • Global CPU interrupt disable mask 1 = All CPU interrupts are disabled • SWI interrupt is non-maskable 0 = CPU interrupts are processed

  5. IRQ Interrupt Flowchart FROM RESET YES I BIT SET? NO YES INTERRUPT? NO STACK CPU REGISTERS. SET I BIT. LOAD PC WITH INTERRUPT VECTOR. FETCH NEXT INSTRUCTION. YES SWI INSTRUCTION? NO RTI YES UNSTACK CPU REGISTERS. INSTRUCTION? NO EXECUTE INSTRUCTION.

  6. V DD IRQ1/Vpp IRQ1 Block Diagram ACK1 CLR Q D SYNCHRO- NIZER IRQ1 INTERRUPT REQUEST CK IRQ1 LATCH IMASK1 MODE1 HIGH VOLTAGE DETECT TO MODE SELECT LOGIC

  7. IRQ1 • Interrupt request is latched on falling edge • Trigger may be edge sensitive only or level and edge sensitive • Maskable through IMASK1 bit • CPU automatically clears request during interrupt processing • Software may optionally clear the request • Vector address is $FFFA and $FFFB (68HC708XL36)

  8. IRQ1 Control READ: 0 0 PIN2 IMASK2 MODE2 IRQ2DIS IMASK1 MODE1 ISCR WRITE: ACK2 ACK1 RESET: 0 0 0 0 0 0 0 0 • IRQ Status and Control Register (ISCR) • IRQ1 edge/level select (MODE1) • Selects trigger sensitivity of the IRQ1 pin 1 = Interrupt requests on falling edges or low levels 0 = Interrupt requests on falling edges only • IRQ1 Interrupt Mask (IMASK1) 1 = IRQ1 Interrupts requests disabled 0 = IRQ1 Interrupts requests enabled • IRQ1 Interrupt request acknowledge (ACK1): write-only • Used to Clear the IRQ1 request Writing logic 1 clears the IRQ latch • Always reads as logic zero.

  9. SYNCHRO- NIZER IRQ2 Block Diagram CONFIGURABLE PORT PINS ACK2 V DD CLR D Q IRQ2DIS CK IRQ2/ KEYBOARD INTERRUPT IRQ2/KEYBOARD IMASK2 REQUEST INTERRUPT LATCH IRQ2 PIN2 MODE2

  10. IRQ2 • Interrupt request is latched on falling edge • Trigger may be edge sensitive only or level and edge sensitive • Maskable through the IMASK2 bit • CPU automatically clears request during interrupt processing • Software may optionally clear the request • Vector address is $FFE0 and $FFE1 (68HC708XL36)

  11. READ: 0 0 PIN2 IMASK2 MODE2 IRQ2DIS IMASK1 MODE1 ISCR WRITE: ACK2 ACK1 RESET: 0 0 0 0 0 0 0 0 IRQ2 Control • IRQ Status and Control Register (ISCR) • IRQ2/Keyboard Interrupt edge/level select (MODE2) • Selects trigger sensitivity of the IRQ2 and Keyboard Interrupt Pins 1 = Interrupt on falling edges or low levels 0 = Interrupt on falling edges only • IRQ2/Keyboard Interrupt Mask (IMASK2) 1 = IRQ2 and Keyboard Interrupts disabled 0 = IRQ2 and Keyboard Interrupts enabled • IRQ2/Keyboard Interrupt request acknowledge (ACK2) • Used to Clear the IRQ2/Keyboard requests Writing logic 1 acknowledges the request • ACK2 always reads as logic zero • IRQ2 Pin Interrupt Latch Disable (IRQ2DIS) • Prevents the IRQ2 pin from latching interrupt requests into the IRQ2/Keyboard interrupt latch 1 = IRQ2 pin interrupt requests not latched 0 = IRQ2 pin interrupt requests latched • IRQ2 Pin state (PIN2) • Reflects the current level of the IRQ2 pin • Can be used to distinguish between Port interrupt and an actual IRQ2 interrupt • 1 = IRQ2 pin at logic one • 0 = IRQ2 pin at logic zero

  12. TO PTD0 PULL-UP ENABLE SYNCHRO- TO PTD7 NIZER PULL-UP ENABLE Configurable Port Interrupts Block Diagram PTD0/KBD0 . . KB0IE . ACK2 V DD PTD7/KBD7 CLR D Q IRQ2DIS CK IRQ2/ KB7IE KEYBOARD INTERRUPT IRQ2/KEYBOARD IMASK2 REQUEST INTERRUPT LATCH IRQ2 PIN2 MODE2

  13. Keyboard Interrupt Pins • Port D pins can be enable as port interrupts • Interrupt requests are latched into the IRQ2/Keyboard Interrupt Latch • Interrupt request is latched on falling edge • Trigger may be edge sensitive only or level and edge sensitive • Generate an IRQ2 interrupt request • Vector address is $FFE0 and $FFE1 (68HC708XL36)

  14. READ: KB7IE KB6IE KB5IE KB4IE KB3IE KB2IE KB1IE KB0IE KBICR WRITE: RESET: 0 0 0 0 0 0 0 0 Keyboard Interrupt Control • Keyboard Interrupt Control Register (KBICR) • Keyboard Interrupt Enable bits (KB7IE - KB0IE) • Enables corresponding keyboard interrupt pin to latch interrupt request • Port pin data direction automatically changed to input 1 = Corresponding Keyboard interrupt pin enabled and pull-up device on 0 = Corresponding Keyboard interrupt pin disabled and pull-up device off

  15. READ: V 1 1 H I N C Z CCR WRITE: RESET: x 1 1 x 1 x x x READ: KB7IE KB6IE KB5IE KB4IE KB3IE KB2IE KB1IE KB0IE KBICR WRITE: RESET: 0 0 0 0 0 0 0 0 Summary READ: 0 0 PIN2 IMASK2 MODE2 IRQ2DIS IMASK1 MODE1 ISCR WRITE: ACK2 ACK1 RESET: 0 0 0 0 0 0 0 0