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Advanced Mass Memory System for Data Acquisition in Scientific Applications

This document outlines the development and design of a high-capacity mass memory system by Robert Abiad, suitable for data storage from multiple sensors including imagers, photometers, and spectrophotometers. Supporting a data rate of up to 8M pixels/s, the memory architecture uses Samsung's K4S560832A-TL1H chip for efficient read/write operations, encompassing error correction capabilities. The system is currently in the debugging phase, with interface tests planned. Key features include 2.6 Gbits memory structured for optimal performance and radiation-hardening for durability.

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Advanced Mass Memory System for Data Acquisition in Scientific Applications

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  1. ISUAL Mass Memory Robert Abiad

  2. Outline • Description • Requirements • Interfaces • Block Diagram • Usage Scheme • Parts • Development Status NCKU UCB Tohoku Mass Memory R. Abiad

  3. Description • 2.6 GBits organized as 64 M x 40 bits • 32 bit data word after EDAC • 7 bit Error Correction Code per word corrects all single bit errors and detects all double bit and some multiple bit errors. • Base device is Samsung K4S560832A-TL1H 256 Mbit chip organized as 32M x 8bits. NCKU UCB Tohoku Mass Memory R. Abiad

  4. Requirements • Store data from Imager at 8M pixels/s data rate • Store data from Array Photometer at 20k samples/s x 32 channels/sample = 640k channels/s • Store data from Spectrophotometer at 10k samples/s x 6 channels/sample = 60k channels/s • Read telemetry data at 1.6 Mb/s • Allow read/write from DPU • Allow read/write from DCM NCKU UCB Tohoku Mass Memory R. Abiad

  5. Mass Memory Interfaces IDC/ Mass Memory ACQUIRE Imager 12 DATA CLK DATA 2 SP CLK 2 STB 2 CTS Telemetry DATA-1 AP CLK DATA-2 DATA CLK RTS STB DATA DPU CMD0 CMD1 CLK 32 DATA DCM ADDR 26 MBUSY R/W 2 NCKU UCB Tohoku Mass Memory R. Abiad

  6. Priorities • Imager • Memory Refresh • Telemetry • Array Photometer • Fast Spectrophotometer • Slow Spectrophotometer • DPU • DCM NCKU UCB Tohoku Mass Memory R. Abiad

  7. Mass Memory Block Diagram Imager Data Interface 32MB SDRAM 32MB SDRAM AP SP DPU 32MB SDRAM 32MB SDRAM DCM Level Shift TLM 32MB SDRAM 32MB SDRAM Address Interface 32MB SDRAM 32MB SDRAM Level Shift 32MB SDRAM 32MB SDRAM NCKU UCB Tohoku Mass Memory R. Abiad

  8. Usage Scheme A A • Circular buffers • Fill on trigger • M Pretrigger • N Posttrigger • Buffer switch Buffer Allocation M Trigger N B Buffer Allocation NCKU UCB Tohoku Mass Memory R. Abiad

  9. SAMSUNG SDRAM • Latch up immune up to 82 MeV/(mg/cm²) • Radiation hardened to 17-40 kRad total dose • Radiation study done by Innovative Concepts, Inc. • No total dose issues • SEU rate of ~100 events/day • Uncorrectable error rate of ~4/day NCKU UCB Tohoku Mass Memory R. Abiad

  10. Development Status • Engineering unit designed and built • Actel 85% done • Board powered up • Currently debugging • First tests to be done with DPU • Interface tests planned with Imager and DCM NCKU UCB Tohoku Mass Memory R. Abiad

  11. Schematics Page 1 NCKU UCB Tohoku Mass Memory R. Abiad

  12. Schematics Page 2 NCKU UCB Tohoku Mass Memory R. Abiad

  13. Schematics Page 3 NCKU UCB Tohoku Mass Memory R. Abiad

  14. Schematics Page 4 NCKU UCB Tohoku Mass Memory R. Abiad

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