ECE 124a/256c MOS Gate Models

1. ECE 124a/256cMOS Gate Models Forrest Brewer Displays: W. Burleson, K. Bernstein, P. Gronoski

2. Basics (MOS Electrical Model) • Nonlinear model with 3 conduction modes: • Linear Mode (Vds < Vgs-VT) and (Vds < Vsat): VF = Vds • Saturation (Vds > Vgs-VT) and (Vds < Vsat): VF = Vgs-VT • Velocity Saturation (Vds > Vsat): VF = Vsat • VF = Min(Vgs-VT,Vsat, Vds )

3. Body Effect • Threshold is function of back potential • Increases difficulty of turn on for junction reverse bias increase

4. Velocity Saturation • Carrier Velocity Saturates at about 1.7x107cm/s • For short channel (small L) this occurs at Vsat • Mobility (m) is a function of doping and temperature

5. MOS Capacitors • Gate (assume constant) = eSi WL/tox • Source/Drain • Bottom (Area) CJ mJ • SideWall (Perimeter) CJSW mJSW • Equivalent Capacitance (Swing Vlow to Vhigh)

6. G C C GD GS S D C GB C SB C DB B Transient Capacitor Parasitics • Only capacitors which change potential over the swing are included. • Cgs and Cgd are often modeled as Cg and Cgso, Cgdo. Cgdo models the feed though (input to output) capacitance • For low swing rates, double Cgdo • For high swing rates, start the output swing from the offset output voltage • Cgdo and Cload produce a capacitive voltage divider.

7. Static Complementary CMOS VDD In1 PMOS only In2 PUN … InN F(In1,In2,…InN) In1 In2 PDN … NMOS only InN PUN and PDN are logicallydual logic networks

8. 1.8 1.7 1.6 1.5 1.4 (V) 1.3 M V 1.2 1.1 1 0.9 0.8 0 1 10 10 /W W p n Inverter Threshold vs. N/P Ratio

9. 0 -2 -4 -6 -8 gain -10 -12 -14 -16 -18 0 0.5 1 1.5 2 2.5 Inverter Gain

10. CMOS Inverter Propagation Delay V DD t = C V /2 pHL L swing I av V out I C L av V = V in DD

11. Approximating Iavg • Prescription from Hodges and Jackson • Assume input rise is instantaneous: ignore rise-time effects • Average charging current at endpoints of swing • Initial point is usually a supply rail, final point is threshold of next gate Iinitial (@ Vout = Vinit) Actual Current Ich Ifinal (@Vout = Vfinal) Vout

12. Hodges-Jackson Current Averaging • FET’s act as a current source • Simple model for full-swing current: • I1 is initial current at start of swing • I2 is current at threshold of next stage • Iavg is approximated by (I1+I2)/2 • Delay

13. 3 2.5 2 tpHL tpLH 1.5 (V) out V 1 0.5 0 -0.5 0 0.5 1 1.5 2 2.5 t (sec) -10 x 10 Transient Response

14. Constructing a Complex Gate • Logic Dual need not be Series/Parallel Dual • In general, many logical dual exist, need to choose one with best characteristics • Use Karnaugh-Map to find good duals • Goal: find 0-cover and 1-cover with best parasitic or layout properties • Maximize connections to power/ground • Place critical transistors closest to output node • Know the order of arrival of signals! – order the transitions if possible (a) pull-down network SN1 SN4 D SN3 SN2 F F A D B D (c) complete gate C C F B A B C (b) Deriving the pull-up network hierarchically by identifying sub-nets D A A B C V V DD DD

15. Example: Carry Gate • F = (ab+bc+ac)’ • Carry ‘c’ is critical • Factor c out: (Why c?) • F=(ab+c(a+b))’ • 0-cover is n-pull up • 1-cover is p-pull down

16. Example: Carry Gate (2) • Pull Down is easy • Order by maximizing connections to ground and critical transistors • For pull up – Might guess series parallel graph dual– but would guess wrong

17. Example: Carry Gate (3) • Series/Parallel Dual • 3-series transistors • 2 connections to Vdd • 7 floating capacitors

18. Example: Carry Gate (4) • Pull Up from 1 cover of Kmap • Get a’b’+a’c’+b’c’ • Factor c’ out • 3 connections to Vdd • 2 series transistors • Co-Euler path layout • Moral: Use Kmap!

19. Euler Path • For CMOS standard cell, and Euler path often helps to organize the transsistor order so that a faster, more dense cell can be constructed. • Ideally, the p-fet and n-fet sub-circuits can be traversed in identical transistor orders to create a layout without diffusion (thinox) gaps. • Euler Path: • Traversal of entire schematic (every transistor) without traversing any transistor twice. • Possible only if 0 or 2 odd nodes in schematics. Node count is the number of transistors incident on a common point. • If 0, any point can be start (will also be end) of path, for 2, one of the odd nodes is the start and the other is the end.

20. b a a c b f' b c a b a b c a b a X X X X X X X X X X Euler Path II • Eg. Carry Gate • Path: b-a-c-b-a or a-b-c-a-b or … • Can sometimes also minimize the routing by careful choice of order

21. Static Logic: Rules of Thumb • Step-up (alpha) ratio of 4 produces minimum power-delay product • P vs. N (beta) ratio of 2 balances pull-up and pull-down times and noise margins. • Approximately 75% of static logic are NAND stacks (limit stack to 3-4, use ordering and tapering for speed)

22. More Rules of Thumb • Glitches consume approximately 15% of overall chip power. • Crossover (short-circuit) current consumes ~ 10% of a static chip’s total power (but is a function of input/output slews, ie sizing)

23. V V V DD DD DD Resistive Depletion PMOS Load V < 0 R Load Load T L V SS F F F In In In 1 1 1 In In In PDN PDN PDN 2 2 2 In In In 3 3 3 V V V SS SS SS (a) resistive load (b) depletion load NMOS (c) pseudo-NMOS Ratio Logic Goal: to reduce the number of devices over complementary CMOS as a means to reduce parasitics (usually for performance).

24. Pseudo NMOS

25. Even Better Noise Immunity/Density V V DD DD M1 M2 Out Out A A PDN1 PDN2 B B V V SS SS Differential Cascode Voltage Switch Logic (DCVSL)

26. DCVSL Example

27. 2.5 1.5 0.5 -0.5 0 0.2 0.4 0.6 0.8 1.0 DCVSL Transient Response A B [V] e A B g a t l o A , B V A,B Time [ns]

28. Complementary Pass Gate Logic (CPL)

29. Pass-gate Logic issues • Limited fan-in • Excessive fan-out • Noise vulnerability (not restoring) • Supply voltage offset/bias vulnerability • Decode exclusivity (else short-circuit!) • Poor high voltage levels if NMOS-only • Body effect

30. Pass-Gate Logic Rules of Thumb • Pass-logic may consume half the power of static logic. But be careful of Vt drop resulting in static leakage. • Pass-gate logic is not appropriate when long interconnects separate logic stages or when circuits have high fan-out load (use buffering).

31. Dynamic Logic • Idea – use the low leakage of FETs to store charge instead of moving current. Provides higher density, faster operation at the cost of reduced noise immunity and tricky design… • Domino is by far the most common style in CMOS

32. Domino logic (single and dual-rail)

33. Dynamic Logic Rules of Thumb • Dynamic logic is best for wide OR/NOR structure (e.g. bit-lines), providing 50% delay improvement over static CMOS. • Dynamic logic consumes 2x power due to its phase activity (unconditional pre-charging), not counting clock power.

34. Domino Rules of Thumb • Typical domino keepers have W/L = 5-20% of effective width of evaluate tree. • Typical domino output buffers have a beta ratio of ~ 6:1 to push the switch point higher for fast rise-time but reduced noise margin.

35. Conventional and Delay-precharge domino

36. Advanced Domino Logic forms

37. Concerns in Dynamic Logic • Charge-sharing • Charge-leakage • Interconnect coupling • Back-gate coupling • Supply noise and variation

38. Back-gate coupling

39. Manchester Carry Chain

40. Discharge Transistor R R R R R R Out 1 2 4 5 6 3 1 2 3 4 5 6 M M M M M M C 0 1 2 3 4 C C C C C C 1 2 3 4 5 6 400 25 300 20 d e a e 200 15 e p r S A 100 10 0 5 1 1.5 2.0 2.5 3.0 1 1.5 2.0 2.5 3.0 k k Speed (normalized by 0.69 RC ) Area (in minimum size devices) Sizing the Manchester Carry Chain

41. Domino Nor16 (zero-detect)

42. Flip-flops/latches/state elements • Flip-flops occupy a special place in conventional digital design • Always Dynamic Behavior • Allow time coherence across large parts of the circuit • Preserve data across synchronization boundaries • --Inherently asynchrnous design

43. Level-sensitive latch pair

44. Modified Svensson Latch of 21064

45. Tri-state based static latch

46. Master-slave (Dynamic) FF

47. Sense Amplifier-Based Flip-Flop Courtesy of IEEE Press, New York.  2000

48. Sense Amplifier-Based Flip-Flop The first stage is unchanged sense amplifier Second stage is sized to provide maximum switching speed Driver transistors are large Keeper transistors are small and disengaged during transitions

49. On-chip Memory • Typically largest fraction of chip area • Nearly always topologically organized (low Rent parameter <0.6) • Simple wire/area planning rules

50. Generic memory block diagram