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Comprehensive Overview of RFID Tag Chip Design and Circuit Architectures

This chapter delves into the intricacies of RFID tag chip design, including system architecture and the Gen2 protocol's frame-sync sequence. It highlights power generation through multi-level voltage systems and elucidates N-stage Dickson charge pumps. Key factors affecting power conversion efficiency are discussed alongside variations of charge pump circuits featuring self-threshold and dynamic compensation. The chapter also presents innovative CMOS architectures, sense amplifiers, and energy-efficient adiabatic circuits, along with practical examples and schematic representations.

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Comprehensive Overview of RFID Tag Chip Design and Circuit Architectures

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  1. Chapter 4 – RFID tag chip design

  2. Figure 4.1 Tag system architecture

  3. Figure 4.2 The “frame-sync” sequence of Gen2 protocol

  4. Figure 4.3 Multi-level supply voltage generation

  5. Figure 4.4 An N-stage Dickson charge pump

  6. Figure 4.5 The factors affecting the power conversion efficiency of the charge pump

  7. Figure 4.6 Charge pump circuit with self-threshold compensation

  8. Figure 4.7 Charge pump circuit with constant threshold compensation and substrate shift

  9. Figure 4.8 Symmetrical charge pump circuit with dynamic threshold compensation

  10. Figure 4.9 Oscillator based TRNG

  11. Figure 4.10 Logical memory map（redrawn from ISO 18000-6C.）

  12. Figure 4.11 Basic single-end SPNVM cell structure

  13. Figure 4.12 Schematic (a) control capacitor Mc and tunneling capacitor Mt (b) cross section

  14. Figure 4.13 General standard CMOS eNVM architecture

  15. Figure 4.14 (a)Voltage-mode sense amplifier (b) Current-mode sense amplifier

  16. Figure 4.15 Block diagram of RFID tag baseband

  17. Figure 4.16 Decode Margin for 1.28 MHz with 5% clock uncertainty (violations marked with the circle)

  18. Figure 4.17 Decode Margin for 1.92 MHz with 5% clock uncertainty

  19. Figure 4.18 BLF error when clock rate is 1.28 MHz (violations marked with the circle)

  20. Figure 4.19 BLF error when clock rate is 1.92 MHz

  21. Figure 4.20 Clock Gating

  22. Figure 4.21 Example of adiabatic CMOS circuit (left) versus standard CMOS Logic (right)

  23. Figure 4.22 Energy dissipation in the adiabatic circuit

  24. Figure 4.23 The different package of on-chip antenna and tag chip

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