FIFO Chip Design Example

1. FIFO Chip Design Example EE166 SJSU David Parent EE166 FIFO Example

2. FIFO Example • We will now try to put together the concepts of: • Cell based design • Super Buffer • Clock trees • IP reuse • Getting a chip into a Pad frame • FIFO • Simple, Regular EE166 FIFO Example

3. Getting Started • The first thing we must do is decide the pins in an actual pad frame with the package. • This will give us the context we need to make intelligent decisions about routing. EE166 FIFO Example

4. MOSIS Pad frame • The stand tiny chip from MOSIS can support 40 pins. • You need to start with the pin out of the actual packaged chip to make the part useable and testable. • We will use pin 1 as VDD and 21 as GND as a standard. This inputs will come in the top (2-20) and out puts in general will be out the bottom (21-40) • We will choose pin 2 for CK, 3 for NPRE and 4 for NCLR • A0-A15 will map to pins 5-20. • Y0-Y15 will map to pins 40-25. EE166 FIFO Example

5. Packaged Part Note: I will not fab a part without the pins list! EE166 FIFO Example

6. Sample Pad frame Area inside is 895mm by 895mm. pin 21 pin 1 You can get more area buy using less pins. (Read Data in serially?) You can have larger circuits but they use up more “MOSIS money” EE166 FIFO Example

7. Bonding Diagram This goes in the package. EE166 FIFO Example

8. How big a FIFO can we make? • Our DFF is 72mm x 36mm in area • A MOSIS tiny chip gives you about 900mm x 900mm of space Assume that we can only use ½ the space. • This can be increased if you use less than 40 pads. • Number of rows 450/36 gives 12 • Number of columns 900/72 gives 12 EE166 FIFO Example

9. We could get rid of not clock by adding an inverter and save 3mm. Saving Space We could overlay the clock and reset signals and save 10mm. We could overlay the ground wires and save 3 mm. EE166 FIFO Example

10. Trade offs • Replacing not clock with an inverter. • New Cell Height 33 (450/33 gives 13) • New Cell Width 72+8 (900/ gives 11) • Routing is easier • Do not have to worry about skew between not clock and clock • Will the power go up? • Maybe. You would need another super buffer to drive not clock. In this case you only need one. EE166 FIFO Example

11. Trade offs • Overlay the reset and clock signals • New average Cell Height 31 (450/31 gives 14) • No New Cell Width • Need two DFF parts one flipped with different wiring to the global signals one unchanged • We already need two type of FF one with D and not D and the other with D input only. This would make 4 different FF! EE166 FIFO Example

12. Trade offs • Overlay the ground signals • New average Cell Height 34.5 (450/34.5 gives 13) • No New Cell Width • Electro migration? • Nothing works! • We have to try it all! • Still only 15 wide! • We could shrink height by 3mm which would give us 16 bits wide but then AOI logic would not fit into the cell height. • We beg the senior engineer for 50mm more space. EE166 FIFO Example

13. 20 min 40 min 4 DFF’s • All The FFs need to have the Not clock removed! • Need to have to verify 4 new parts from one old part! • This will take some time! • No choice. • New Average Cell Height 31.375 16 bits high will give less than 500 microns so it it will fit in the expanded space. 5 min 7 min EE166 FIFO Example

14. Derivative DFF Design It also helped that my NAND3 was designed to have flexible routing, rather than minimum area. I really saved some time by reusing the same template. EE166 FIFO Example

15. Not D Internal Routing Up • Not CK are provided by inverters to be added as required. Not D is generated by the NAND2 from D. Since we will not be operating at less than 1ns the increase setup time will not matter. EE166 FIFO Example

16. NPRE NCLR CK DFF_DI_RU Use the nand as an inverter. Q QN D EE166 FIFO Example

17. DFF_DI_RD CK NPRE NCLR EE166 FIFO Example

18. DFF_DE_RU EE166 FIFO Example

19. DFF_DE_RU D ND EE166 FIFO Example

20. DFF_DE_RD Q QN D ND EE166 FIFO Example

21. DFF_INV EE166 FIFO Example

22. Design Review • After looking at the parts so far it looks like there could be an electro migration problem where the VDD is bought into the circuit Since all the FF use the same basic parts, We just have to fix it once in each cell. You can even edit it in place! I had to flatten the NTAP to do this. I had to add some nwell due to a DRC error. EE166 FIFO Example

23. New DFF Structure EE166 FIFO Example

24. Back to the FIFO • We can fit 16 bits high within 500 microns • We can fit 900/80 long (11) • We can do a FIFO 10 bits deep. • We will use 16 x 10 DFF (160) • 8 DFF_DI_RU • 8 DFF_DI_RD • 72 DFF_DE_RU • 72 DFF_DE_RD EE166 FIFO Example

25. Gut check on power • 160 DFF • Each one has 21 NMOS and 21 PMOS • This is like having 21 inverters • Total number of inverters is 3360 (6720 transistors) • The power for one inverter at 30 Mhz is The power for an alfa of one and 3360 Inverters is 58mW We know that not all transistors do not switch every clock cycle so this is an upper bound. EE166 FIFO Example

26. 30 MHz! What happened to 200MHz? • With no PLL and the data coming from off chip the maximum clock rate and off chip speed is about 30 MHz! One could design special output buffers but these are tricky and would use more power! • We will continue to test at a higher speed because the simulation will go faster! • For the final pin to pin simulation we will have to simulate at 30 MHz for at least 20 clock periods. EE166 FIFO Example

27. FIFO Schematic Start off with the basic structure that can be copied and pasted. EE166 FIFO Example

28. FIFO Schematic Hard to see! EE166 FIFO Example

29. FIFO Schematic Complete EE166 FIFO Example

30. FIFO Symbol EE166 FIFO Example

31. Verilog takes less than a second to verify. EE166 FIFO Example

32. Verilog Test bench EE166 FIFO Example

33. Spice Test Bench EE166 FIFO Example

34. Input Vectors EE166 FIFO Example

35. Input Vectors EE166 FIFO Example

36. Input Vectors EE166 FIFO Example

37. Output EE166 FIFO Example

38. Output EE166 FIFO Example

39. Spice Summary • The circuit’s has been validated • The simulation took about 10 minutes to run! EE166 FIFO Example

40. Pre Rout CK NPRE and NCLR Layout Set up The first 4 FF Then make it 10 across EE166 FIFO Example

41. Layout with only cells EE166 FIFO Example

42. Route VDD and Ground EE166 FIFO Example

43. GND Final FIFO Layout VDD DATA FLOW EE166 FIFO Example

44. Final Layout Verification EE166 FIFO Example

45. Post Extraction Simulation EE166 FIFO Example

46. Modify a Pad frame • The parts we need are: • input buffer (padinc) • output buffer (padio) • corners (fc) • VDD pad (padvdd) • GND pad (paddgnd) • You can FTP a sample pad frame from mosis: • http://www.mosis.org/Technical/Designsupport/pad-library-scmos.html • The Docs are there as well. EE166 FIFO Example

47. Sample Padframe Load in a sample padframe. To change a pin just select it and press q for edit, and then change the same to what you want. EE166 FIFO Example

48. Change Pin 21 from padinc to padgnd padinc to padgnd EE166 FIFO Example

49. Make sure pads abut. correct But Metal 1 together and make sure the PSEL line is on he horizontal axis. Not correct! Pin 26 EE166 FIFO Example

50. Change pins 22-24 to unused EE166 FIFO Example