1. Chip design • MSU responsibility – full chip or part of it • Design Kits - how to get it? CERN? MSU? WHO? • Who will manage the development from CERN side • How to obtain CERN building blocks • Cadence 5 or Cadence 6 • What the procedure to create the chip architecture (MSU? CERN) - meetings/EVO, regular meetings (1 per month, 1 per 2 months) • Schematics –max. new

2. Conception • Conception of Electronics Architecture seems to be realistic • Do we need additional parameters which should been sent to FE (Main things described)? • FE chip should consists of: analog part, ADC, ZS (programmable), Bcnt, config., buffer. Block and interfaces. Synhro 40 MHz. FE Reset, Test pulse, DCnt reset (perhaps something more), transmission data without ZS for testing, min readout delay, no data to out if buffer is full. • Question –why ZS has fluctuation

3. Conception • Data structure word consists of header band data • Some useful things are in conception as well< we should combine them for the chip specification • Monitoring ZS fluctuation (how) and buffer. • ZS algorithm • Masking noisy and bad channels

4. Schematics • A lot of questions for some presentation – what is still actual: • SAR ADC • About front-end submicron technologies • ADCN-25 • Protocols • Other chips for LHC

5. Specification • Sensor thickness • Sensor pitch • Sensor capacitance • MIP level • AC or DC coupling (max dark current) • Single or Double side sensors • Signal/noise, slope • Gain • Dead time • Peaking time

6. Specification • Linearity • Dynamic range • ADC Bits • Time resolution • Gain stability • Other parameters stability • Radiation hardness • Structure detailed • Power consumption • Supply voltage

7. Specification • Number of channel • Pedestal parameters (stability) • Connection between chip and detector • Chip geometry • Chip technology • Base line stability • Interfaces • Protection • Load • Out levels

8. Specification • Pin definition • Occupancy • Time walk • SEU • Adjustment • Description how to work the final structure