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Microfluidic Chips

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85 diapositives · 1.1K Views · Jul 15, 2012

Bringing Programmability to Experimental Biology Bill Thies Joint work with Vaishnavi Ananthanarayanan, J.P. Urbanski , Nada Amin, David Craig, Jeremy Gunawardena , Todd Thorsen , and Saman Amarasinghe Microsoft Research India ICIP 2011. Microfluidic Chips.

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Microfluidic Chips
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  1. Bringing Programmability toExperimental BiologyBill ThiesJoint work with Vaishnavi Ananthanarayanan, J.P. Urbanski, Nada Amin, David Craig, Jeremy Gunawardena, Todd Thorsen, and Saman AmarasingheMicrosoft Research IndiaICIP 2011

  2. Microfluidic Chips • Idea: a whole biology lab on a single chip • Input/output • Sensors: pH, glucose, temperature, etc. • Actuators: mixing, PCR, electrophoresis, cell lysis, etc. • Benefits: • Small sample volumes • High throughput • Applications: • Biochemistry - Cell biology • Biological computing 10x real-time 1 mm

  3. Application to Rural Diagnostics DxBox U. Washington,Micronics, Inc., Nanogen, Inc. Targets: - malaria (done) - dengue, influenza,Rickettsial diseases, typhoid, measles (under development) Disposable EntericCard PATH,Washington U.Micronics, Inc., U. Washington Targets: - E. coli, Shigella, Salmonella, C. jejuni CARD Rheonix, Inc. Targets: - HPV diagnosis - Detection of specific gene sequences

  4. Moore’s Law of Microfluidics:Valve Density Doubles Every 4 Months Source: Fluidigm Corporation (http://www.fluidigm.com/images/mlaw_lg.jpg)

  5. Moore’s Law of Microfluidics:Valve Density Doubles Every 4 Months Source: Fluidigm Corporation (http://www.fluidigm.com/didIFC.htm)

  6. Current Practice: Manage Gate-Level Details from Design to Operation • For every change in the experiment or the chip design: fabricate chip 2. Operate each gate from LabView 1. Manually draw in AutoCAD

  7. Abstraction Layers for Microfluidics Silicon Analog Protocol Description Language - architecture-independent protocol description C Fluidic Instruction Set Architecture (ISA) - primitives for I/O, storage, transport, mixing x86 Pentium III,Pentium IV chip 1 chip 2 chip 3 transistors, registers, … Fluidic Hardware Primitives - valves, multiplexers, mixers, latches

  8. Abstraction Layers for Microfluidics Contributions Protocol Description Language - architecture-independent protocol description BioCoder Language [J.Bio.Eng. 2010] Optimized Compilation [Natural Computing 2007] Fluidic Instruction Set Architecture (ISA) - primitives for I/O, storage, transport, mixing Demonstrate Portability [DNA 2006] Micado AutoCAD Plugin [MIT 2008, ICCD 2009] chip 1 chip 2 chip 3 Digital Sample Control Using Soft Lithography [Lab on a Chip ‘06] Fluidic Hardware Primitives - valves, multiplexers, mixers, latches

  9. Primitive 1: A Valve (Quake et al.) Control Layer Flow Layer

  10. Primitive 1: A Valve (Quake et al.) Control Layer Flow Layer

  11. Primitive 1: A Valve (Quake et al.) Control Layer Thick layer (poured) Thin layer (spin-coated) Flow Layer

  12. Primitive 1: A Valve (Quake et al.) Control Layer Flow Layer

  13. Primitive 1: A Valve (Quake et al.) Control Layer Flow Layer

  14. Primitive 1: A Valve (Quake et al.) Control Layer Flow Layer

  15. Primitive 1: A Valve (Quake et al.) Control Layer Flow Layer

  16. Primitive 1: A Valve (Quake et al.) Control Layer pressure actuator Flow Layer

  17. Primitive 2: A Multiplexer (Thorsen et al.) flow layer control layer Bit 2 Bit 1 Bit 0 1 1 1 0 0 0 Output 7 Output 6 Output 5 Input Output 4 Output 3 Output 2 Output 1 Output 0

  18. Primitive 2: A Multiplexer (Thorsen et al.) flow layer control layer Bit 2 Bit 1 Bit 0 1 1 1 0 0 0 Output 7 Output 6 Output 5 Input Output 4 Output 3 Output 2 Output 1 Output 0 Example: select 3 = 011

  19. Primitive 2: A Multiplexer (Thorsen et al.) flow layer control layer Bit 2 Bit 1 Bit 0 1 1 1 0 0 0 Output 7 Output 6 Output 5 Input Output 4 Output 3 Output 2 Output 1 Output 0 Example: select 3 = 011

  20. Primitive 2: A Multiplexer (Thorsen et al.) flow layer control layer Bit 2 Bit 1 Bit 0 1 1 1 0 0 0 Output 7 Output 6 Output 5 Input Output 4 Output 3 Output 2 Output 1 Output 0 Example: select 3 = 011

  21. Primitive 3: A Mixer (Quake et al.) 1. Load sample on bottom 2. Load sample on top 3. Peristaltic pumping Rotary Mixing

  22. Abstraction Layers for Microfluidics Protocol Description Language - architecture-independent protocol description Fluidic Instruction Set Architecture (ISA) - primitives for I/O, storage, transport, mixing chip 1 chip 2 chip 3 Fluidic Hardware Primitives - valves, multiplexers, mixers, latches

  23. Driving Applications 1. What are the best indicators for oocyte viability? • With Mark Johnson’s andTodd Thorsen’s groups • During in-vitro fertilization, monitor cell metabolites and select healthiest embryo for implantation 2. How do mammalian signal transduction pathways respond to complex inputs? • With Jeremy Gunawardena’sand Todd Thorsen’s groups • Isolate cells and stimulate with square wave, sine wave, etc.

  24. CAD Tools for Microfluidic Chips • Goal: automate placement, routing, control of microfluidic features • Why is this different than electronic CAD?

  25. CAD Tools for Microfluidic Chips • Goal: automate placement, routing, control of microfluidic features • Why is this different than electronic CAD? 1. Control ports (I/O pins) are bottleneck to scalability • Pressurized control signals cannot yet be generated on-chip • Thus, each logical set of valves requires its own I/O port 2. Control signals correlated due to continuous flows  Demand & opportunity for minimizing control logic pipelined flow continuous flow

  26. Our Technique:Automatic Generation of Control Layer

  27. Our Technique:Automatic Generation of Control Layer 1. Describe Fluidic ISA

  28. Our Technique:Automatic Generation of Control Layer 1. Describe Fluidic ISA

  29. Our Technique:Automatic Generation of Control Layer 1. Describe Fluidic ISA

  30. Our Technique:Automatic Generation of Control Layer 1. Describe Fluidic ISA 2. Infer control valves

  31. Our Technique:Automatic Generation of Control Layer 1. Describe Fluidic ISA 2. Infer control valves

  32. Our Technique:Automatic Generation of Control Layer 1. Describe Fluidic ISA 2. Infer control valves 3. Infer control sharing

  33. Our Technique:Automatic Generation of Control Layer 1. Describe Fluidic ISA 2. Infer control valves 3. Infer control sharing

  34. Our Technique:Automatic Generation of Control Layer 1. Describe Fluidic ISA 2. Infer control valves 3. Infer control sharing 4. Route valves to control ports

  35. Our Technique:Automatic Generation of Control Layer 1. Describe Fluidic ISA 2. Infer control valves 3. Infer control sharing 4. Route valves to control ports

  36. Our Technique:Automatic Generation of Control Layer 1. Describe Fluidic ISA 2. Infer control valves 3. Infer control sharing 4. Route valves to control ports

  37. Our Technique:Automatic Generation of Control Layer 1. Describe Fluidic ISA 2. Infer control valves 3. Infer control sharing 4. Route valves to control ports 5. Generate an interactive GUI

  38. Our Technique:Automatic Generation of Control Layer 1. Describe Fluidic ISA 2. Infer control valves 3. Infer control sharing 4. Route valves to control ports 5. Generate an interactive GUI

  39. Our Technique:Automatic Generation of Control Layer 1. Describe Fluidic ISA 2. Infer control valves 3. Infer control sharing 4. Route valves to control ports 5. Generate an interactive GUI

  40. Our Technique:Automatic Generation of Control Layer 1. Describe Fluidic ISA 2. Infer control valves 3. Infer control sharing 4. Route valves to control ports 5. Generate an interactive GUI

  41. Routing Algorithm • Build on recent algorithmfor simultaneous pin • assignment & routing • [Xiang et al., 2001] • Idea: min cost - max flow • from valves to ports • Our contribution: extend algorithm to allow sharing • – Previous capacity constraint on each edge: • – Modified capacity constraint on each edge: • Solve with linear programming, allowing sharing where beneficial f1 + f2 + f3 + f4 + f5 + f6 ≤ 1 max(f1, f4) + max(f2 , f3) + f5 + f6 ≤ 1

  42. Routing Algorithm • Build on recent algorithmfor simultaneous pin • assignment & routing • [Xiang et al., 2001] • Idea: min cost - max flow • from valves to ports • Our contribution: extend algorithm to allow sharing • – Previous capacity constraint on each edge: • – Modified capacity constraint on each edge: • Solve with linear programming, allowing sharing where beneficial f1 + f2 + f3 + f4 + f5 + f6 ≤ 1 max(f1, f4) + max(f2 , f3) + f5 + f6 ≤ 1

  43. Embryonic Cell Culture Courtesy J.P. Urbanski

  44. Embryonic Cell Culture Courtesy J.P. Urbanski

  45. Cell Culture with Waveform Generator Courtesy David Craig

  46. Cell Culture with Waveform Generator Courtesy David Craig

  47. Metabolite Detector Courtesy J.P. Urbanski

  48. Metabolite Detector Courtesy J.P. Urbanski

  49. Micado: An AutoCAD Plugin • Implements ISA, control inference, routing, GUI export • Using slightly older algorithms than presented here [Amin ‘08] • Parameterized design rules • Incremental construction of chips • Realistic use by at least 3 microfluidic researchers • Freely available at:http://groups.csail.mit.edu/cag/micado/

  50. Open Problems • Automate the design of the flow layer • Hardware description language for microfluidics • Define parameterized and reusable modules • Replicate and pack a primitive as densely as possible • How many cell cultures can you fit on a chip? • Support additional primitives and functionality • Metering volumes • Sieve valves • Alternate mixers • Separation primitives • …