ECE 171 Digital Circuits Chapter 10 Programmable Logic Devices (PLD)

1. ECE 171Digital Circuits Chapter 10Programmable Logic Devices (PLD) Herbert G. Mayer, PSU Status 4/20/2018 Copied with Permission from prof. Mark Faust @ PSU ECE

2. Syllabus Taxonomy of ICs PLDs Fuses PLD Implementation PROMs PLAs PALs GALs References

3. Taxonomy of ICs Design Methodology SML (S small, M medium, L large) • Standard Components by Scale of Integration (SSI, MSI, LSI) • Small, Medium, Large • Off-the-shelf Components • Basic Universal Building Blocks (AND, OR, NAND, NOR, etc.) • Application Specific Standard Parts (ASSP) • Target Specific Application Area, but not Customer Specific! • e.g. Printer Controller, USB Interface IC, HDD I/F • Application Specific IC Parts (ASIC) • Custom Design of IC Targeting Specific Market • Full-custom, standard cell, gate-arrays • e.g. ATI 3D Graphics Engine (ATI is part of AMD since 2006) • Programmable Logic Devices (PLD) • Can be used to implement wide variety designs, in Lab or Field • e.g. FPGA (Field-Programmable Gate Arrays)

4. PLDs • Programmable logic device (PLD) is an electronic component to build reconfigurable circuits • Unlike a logic gate with fixed function, a PLD has no function specified at the time of manufacture • Before a PLD can be used, it must be programmed • Programming a PLD means customizing for a specific purpose • Also called configuring the PLD, or reconfiguring • Configuring consists of “blowing” certain fuses, thus enabling or disabling selected functions • Often initial functions included all options, such as a signal and also its complement, which would not be meaningful! • One of the 2 must be eliminated to create a working device

5. PLDs • Abstract PLD below has inputs a and b, both and their complements are connected to and gates and thus to output o • All have a via (path) over fuses, some of which must be blown to leave only meaningful, defined functions a b o

6. Reason for PLDs • Shortened design time, start with s/t that works • Fast prototyping! • Rapid design changes • Reprogrammable • No masks, jumpers, PCB traces • Decreased PCBreal estate + silicon space on IC • Less space than multiple standard logic packages • Improved reliability • Fewer packages • Fewer external interconnects

7. Types of PLDs Programmable Logic Devices (PLDs) • PROM: Programmable Read Only Memory (1960s) • PLA: Programmable Logic Array [Signetics] (1975) • PAL:TM Programmable Array Logic (1978) • GAL:TM Generic Array Logic • CPLD: Complex PLD • FPGA: Field Programmable Gate Array PALÔ and GALÔ are registered trademarks of Lattice Logic

8. AND-OR-Array Architecture Device type AND array OR array Product term sharing PROM Fixed at factory Programmable Yes PLA Programmable Programmable Yes PAL/GAL Programmable Fixed at factory No

9. Programmable Symbology

10. Programmable Symbology • View Pull up resistors R, consider a, bopen, closed: • Openswitch: Voltage drops across A and B toward ground, not across R, due to no current through R • We call this: equals logic 1 • Closed switch: A and B are grounded, current through R, 0 Volt A and B to ground • We call this: equals logic 0

11. Fuses • Fuses were actual real fuses in early technology • Now they generally are just named fuses! • Can be: fuses, transistor circuits, or SRAM-based • Volatile and nonvolatile • Nonvolatile • UV (ultra-violet erasable) • EE (electrically erasable) • Universal Programming Unit (from manufacturer) • Fuse map • JEDEC standard format (Joint Electronics Device Engineering Council) • Several programs generate (MACHXL, ABEL, CUPL)

12. PLD Implementation Flow of Steps of PLD Design and Manufacture

13. PLD Implementation Schematic Capture • PROM • PLA • PAL/GAL • CPLDs Design Tools Fuse Map HDL Universal Programmer Tool and PLD vendors: Xilinx, Altera, Lattice

14. PROMs Product term sharing

15. PROMs • Express the number of outputs No as function of the number of inputs Ni = n • No = n2 • Adding one PROM input doubles number of outputs! • Careful, engineers! • MaskROM is fully programmed one time at the factory

16. PLA vs. PAL • PLAs and PALs are both programmable logic devices (PLD) that implement combinational circuits • PLA has programmable and-gate array, plus programmableor-gate array • PAL has programmableand-gate array, plus a fixedor-gate array -newer, yet more restricted! • As a result, PLAs are slower (longer path), harder to implement, more expensive: more silicon real-estate • Detail on both below . . . • Becoming obsolete, in favor of programmability!

17. PLAs • Programmable logic arrays (PLA) are PLD used to implement a specific combinational circuits • PLA consists of and-gate planes with 2nand-gates for n inputs • Linked to or-gate planes producing m output outputs signals • Allows generation of sums of products of input signals • PLAs offer more flexibility vs. PALs by allowing programmable and-gate and or-gate planes!

18. Generic PLA

19. PLA

20. PALs • Programmable arrayslogic (PAL): also technology used to implement logic functions in silicon • Introduced 1978 by Monolithics Memories Inc. (MMI); now Lattice semiconductors in Oregon • MMI trademarked the term PAL • PALs consist of small PROMs plus added output logic to implement any desired logic function • Using specialized machines, PAL devices were field-programmable: in end-customer lab!

21. PALs PALs come in several variants: • One-time programmable (OTP) devices could not be updated after initial programming • MMI offered a similar family called HAL, or "hard array logic", which were like PAL devices mask-programmed at factory • UV erasable versions had a quartz window over the chip die: To erase for re-use with an ultraviolet light source; like EPROMs • Later versions (e.g.: PALCE22V10) were flash erasable devices

22. PALs • Flash Erasable PAL: type of non-volatile storage device (similar to EE Prom), where erasing can be done, but done by block • Not by individual datum; hence restricted flexibility! • Superseded in late 1990 by FEPROMs that could be re-written, some fixed but large number of times

23. PALs/GALs

24. PAL Function Sharing via Additional Inputs

25. PLD Advantages • Short design time • Rapid prototyping! • Rapid design changes • Reprogrammable • No masks, jumpers, PCB traces • Decreased PCB “real estate” • Less space than multiple standard logic packages • Improved reliability • Fewer packages, fewer external interconnects

26. PALxxyyzz Nomenclature xx Maximum number of AND array inputs zz Maximum number of dedicated outputs y Type of outputs = Combination, Registered, or Versatile Combinational H active high L active low P programmable C complementary Registered R registered RP registered, with programmable polarity Versatile V programmable as combinational or registered

27. Nomenclature Examples PAL3H2 3 inputs 2 outputs Active H outputs PAL16L8 16 inputs 8 outputs Active L (0s of function) PAL22V10 22 inputs 10 outputs Active L or H (1s or 0s) Versatile

28. PAL

29. GAL Emulate any PAL; Reprogrammable Fuses are non-volatile memory cells

30. CPLDs – Complex PLDs • Complex Programmable Logic Device (CPLD): • Programmable logic device with complexity between PALs and FPGAs • Architectural features of both • Main building block of CPLD is Macrocell • Containing logic, implementing disjunctive normal form (DNF) expressions • Plus specialized logic operations • DNF: A sum of products formula!

31. CPLDs – Complex PLDs

32. A B F1 F2 F3 F4 0 0 1 0 1 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 0 1 0 0 Implement Some Choices Implement F1, F2, F3, F4: F1 = invert A, ignore B F2 = A OR B gate F3 = A NAND B gate F4 = A XOR B gate With Technology of: PROM PLA PAL

33. A B F1 F2 F3 F4 0 0 1 0 1 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 0 1 0 0 Fuse map Address Data 0 A 1 F 2 7 3 4 PROM Implementation NOT, OR, NAND, XOR

34. A B F1 F2 F3 F4 0 0 1 0 1 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 0 1 0 0 PLA Implementation NOT, OR, NAND, XOR

35. A B F1 F2 F3 F4 0 0 1 0 1 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 0 1 0 0 PLA Implementation NOT, OR, NAND, XOR

36. A B F1 F2 F3 F4 0 0 1 0 1 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 0 1 0 0 PAL Implementation NOT, OR, NAND, XOR

37. Logic Conventions • Positive Logic Convention (PLC) • Signals always “active high”; we also say:“asserted high” • Bubble o or negation indicator to show complement • Direct Polarity Indication (DPI) • “mixed logic” notation • Suffix (H) or (L) indicates active high H or active low L • Polarity indicator or wedge to indicate active low L PLC DPI Type of Signal Name Signal Name Signal A or A(H) A(H) or A(L) Active High B or B(H) B(H) or B(L) Active Low

38. Indicator Matching

39. Detailed DPI Example(Direct Polarity Indication)

41. Databook Examples

42. Bibliography • PLD: https://en.wikipedia.org/wiki/Programmable_logic_device • PLA: https://en.wikipedia.org/wiki/Programmable_logic_array • PAL: https://en.wikipedia.org/wiki/Programmable_Array_Logic