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This guide provides an overview of pipelined control signals and data hazards in ALU instructions. It details control signal forwarding from EX to WB stages and explains how to detect when to forward based on register dependencies. Key conditions for detecting EX and MEM hazards are discussed, alongside examples to clarify the detection of data hazards during instruction execution. By understanding these principles, one can effectively manage dependencies and improve pipeline performance in CPU architectures.
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Control Refresher • Here are the control signals that were previously identified:
Control Signals Grouped by Stages pass to EX stage pass to MEM stage pass to WB stage
Control Signal Forwarding • Control signals derived from instruction opcode, as before:
Data Hazards in ALU Instructions • Consider this sequence: sub $2, $1,$3and $12,$2,$5or $13,$6,$2add $14,$2,$2sw $15,100($2) • We can resolve hazards with forwarding, but how do we detect when to forward?
Fwd fromEX/MEMpipeline reg Fwd fromMEM/WBpipeline reg Detecting the Need to Forward • Pass register numbers along pipeline • e.g., ID/EX.RegisterRs = register number for Rs sitting in ID/EX pipeline register • ALU operand register numbers in EX stage are given by • ID/EX.RegisterRs, ID/EX.RegisterRt • Data hazards when 1a. EX/MEM.RegisterRd = ID/EX.RegisterRs 1b. EX/MEM.RegisterRd = ID/EX.RegisterRt 2a. MEM/WB.RegisterRd = ID/EX.RegisterRs 2b. MEM/WB.RegisterRd = ID/EX.RegisterRt
Detecting the Need to Forward • But only if forwarding instruction will write to a register! • EX/MEM.RegWrite, MEM/WB.RegWrite • And only if Rd for that instruction is not $zero • EX/MEM.RegisterRd ≠ 0,MEM/WB.RegisterRd ≠ 0
ALU Operand Selection Value from register fetch in ID stage Value from WB stage Value from ALU execution
Forwarding Paths Select source for $rs Select source for $rt register #s from current instruction $rd # from MEM stage Must select correct operand sources $rd # from EX stage
Conditions for EX Hazard • If ( EX/MEM.RegWrite and • EX/MEM.RegisterRd ≠ 0 and • EX/MEM.RegisterRd = ID/EX.RegisterRs )then • ForwardA = 10 • If ( EX/MEM.RegWrite and • EX/MEM.RegisterRd ≠ 0 and EX/MEM.RegisterRd = ID/EX.RegisterRt ) • thenForwardB = 10 QTP: could BOTH occur with respect to the same instruction?
Conditions for MEM Hazard • If ( MEM/WB.RegWrite and • MEM/WB.RegisterRd ≠ 0 and MEM/WB.RegisterRd = ID/EX.RegisterRs ) • thenForwardA = 01 • If ( MEM/WB.RegWrite and • MEM/WB.RegisterRd ≠ 0 and MEM/WB.RegisterRd = ID/EX.RegisterRt ) • thenForwardB = 01 QTP: could BOTH an EX hazard and a MEM hazard occur with respect to the same instruction?
Double Data Hazard • Consider the sequence: add $1,$1,$2add $1,$1,$3add $1,$1,$4 • Both hazards occur… which value do we want to forward? • Revise MEM hazard condition: • Only forward if EX hazard condition is not true
Revised Conditions for MEM Hazard • If ( MEM/WB.RegWrite and • MEM/WB.RegisterRd ≠ 0 and not ( EX/MEM.RegWrite and • EX/MEM.RegisterRd ≠ 0 and EX/MEM.RegisterRd = ID/EX.RegisterRs )and MEM/WB.RegisterRd = ID/EX.RegisterRs ) • thenForwardA = 01 • If ( MEM/WB.RegWrite and • MEM/WB.RegisterRd ≠ 0 and not ( EX/MEM.RegWrite and • EX/MEM.RegisterRd ≠ 0 and EX/MEM.RegisterRd = ID/EX.RegisterRt ) and MEM/WB.RegisterRd = ID/EX.RegisterRt ) • thenForwardB = 01
