Design + System Drivers Update Design ITWG ITRS Public Conference Hsinchu, 5 Dec 2012

Design + System Drivers UpdateDesign ITWGITRS Public ConferenceHsinchu, 5 Dec 2012

Past Trajectory (2004-2011)1. Increasingly quantitative roadmap2. Increasingly complete driver set3. Increasing MTM content 2011 MTM roadmap RF+AMS Driver continued Updated Drivers (MPU, SoC,…) Upgraded DFM, SL, verification sections Power design technology roadmap 2010 2009 MTM RF+AMS Driver start Updated Consumer SOC and MPU Drivers Upgraded RF+AMS section 2008 MTM extension + iNEMI synch + SW !! MTM extension + iNEMI + SW !! 2007 More Than Moore (MTM) analysis + iNEMI Updated Consumer Stationary, Portable architecture, and Networking Drivers 2006 Consumer Stationary, Portable, Networking Drivers Updated Consumer Stationary, Portable, and Networking Drivers 2005 Consumer Stationary, Portable, Networking Drivers Consumer Stationary, Portable Drivers 2004 Consumer Portable Driver Additional Design Metrics DFM Extension System level extension System Drivers Chapter Driver study Revised Design Metrics DFM extension Revised Design Technology Metrics Revised Design metrics Design Technology metrics Explore Design metrics Design Chapter 2

Work Toward 2013 and Beyond • Design Chapter • Version 2 of the Power-Aware Design Technology roadmap • Version 2 of the 3D IC design technology roadmap • Design technology for More Than Moore fabrics (SW, AMS/RF, MEMS) • Updates of LCP, DFT, Design Verification, Design for Resilience • Design of on-chip memory hits the wall at 16nm HP • System Drivers Chapter • Rethinking the MPU Driver: Core + LLC + “uncore”; microserver class • Revising the SOC-Consumer Portable Driver • Elimination of SOC-Networking, SOC-Consumer Stationary drivers ? • Update of Embedded Memory • Continue development of AMS/RF “sub-driver” of SOC-CP Driver • Cross-TWG • CTSG: node timing pull-in, A-factor updates for FinFET, vertical devices • How will FinFET, UTBB SOI timing change PPA projections? • Renewal of the PIDS HP, LP roadmaps (compact modelinginteraction) • 3D effort with other TWGs

Design Cost Roadmap

Design Power Roadmap

Low-Power Design Technology Roadmap NEW: approximate computing, adaptivity, power gating replacement, dark silicon, extreme heterogeneity, …

NEW in Low-Power Design Tech Roadmap • Approximate Computing • Variable-accuracy computing (e.g., flexibly from 64b 16b) • 4D computing: reconfiguration on the fly • AVS ? (e.g., part of DVFS) Margin reduction? • Adaptivity • Recapture overdesign from wearout, variation margins • Power Gating Replacement • HVT device as power switch hits headroom, area wall  ? • Dark Silicon • “normally-off computing” = “extreme power gating”

“Dark Silicon” Analysis in 2001 ITRS • Power management gap  amount of (switched) logic content in an SOC goes to zero • Challenge: keeping the chip value above zero Today: turn on only 2-6% of logic on SOC !

NEW in Low-Power Design Tech Roadmap • Approximate Computing • Variable-accuracy computing (e.g., flexibly from 64b 16b) • 4D computing: reconfiguration on the fly • AVS ? (e.g., part of DVFS) Margin reduction? • Adaptivity • Recapture overdesign from wearout, variation margins • Power Gating Replacement • HVT device as power switch hits headroom, area wall  ? • Dark Silicon • “normally-off computing” = “extreme power gating” • Extreme Heterogeneity • “coprocessor-dominated architectures” • (pervasive heterogeneity; energy-efficiency from specialization; HW accelerators) • “10 x 10”, “13 dwarves”, … • Intel “accelerators for MPU” vs. Tensilica (or, GPUs, xPUs)

Design Tech for More Than Moore Fabrics • Key areas: SW, AMS/RF, MEMS, 3D / novel packaging • Current design technology still insufficient; must broaden beyond current ideas • New 3D / TSV design flows • New multi-physics modeling, simulation, analysis tools • Example: thermal / mechanical analysis (base station) • Example: MEMS + electrical analysis (mobile gaming) • Example: sensors + signal processing (industrial, medical) • Example: software + HW simulation (data center network)

Memory as a Key Factor in Future DT Chip Array Circuit Bit Cell Gate Device Physical Figure DESN12 Possible Variability Abstraction Levels

Memory as a Key Factor in Future DT Figure DESN8 Variability-Induced Failure Rates for Three Canonical Circuit Types

Memory Design Hits The Wall • SRAM hits a brick wall at ~16nm M1 HP • Area overhead: discrete fin sizing to meet stability targets • Vccmin(SRAM) > Vddmin(logic) due to variability  need assist structures, 8T, or 10T structures for 20nm and beyond • Increased leakage due to increased Vccmin(SRAM) and Vt tradeoffs • eDRAM, L3 (SRAM), L2 (SRAM) subsystem replacements • STT-RAM – density, non-volatility (~low leakage) • FLASH  RRAM • Exploiting 3D integration (monolithic, TSV) schemes • Logic, register files, L1 • Power gating strategies • Backup strategies for retention (transfering data to STT-RAM before power-off) • Implications for memory hierarchy, architecture, design • Different sizing of memory subsystems to reflect the energy/latency tradeoffs • Multi-physics models to analyze Vccmin(SRAM) • Exploiting nonvolatility and fine-grain power gating in logic circuits

Changes to MPU Model * CP – Cost-Performance; HP – High Performance ** L2$ and L1$ is per core

Updated MPU Model: UnCore Scaling • “Uncore” (increasing portion of MPU) consists of: • Memory controller(s) • Graphics and display controller(s) • I/O and bus interface controller(s)

New Drivers Catching Up to “Old” Ones ? • “SoC-ification” of Drivers brings similarities • Need to isolate the parameters driven by each (and only) driver

New Drivers Replacing “Old” Ones ? • Potential future system driver list (Markets dimension) • High performance computing MPU – “Office/Server” • Mobile (Application) MPU – “Consumer Portable” • Low power computing MPU – “Microserver”

SoCMPU Convergence: MicroServers ? • Observation: “mobile” computing SoCscompeting in server space • Beginning to be used in data centers and cloud computing • Extreme core efficiency (active power < 4W, sleep power < 0.5W) • #Cores, frequency scaling similar to conventional MPUs • Microserverproduct class (Calxeda, Marvell, Intel, …)  re-examine the MPU model – or possibly create a new driver ! • Clock frequency growing at 1.5X every 2 years • Number of cores growing at 2X every 4 years • Networking-like SoC scaling: off-chip latency, accelerators, L3 cache • Power budget under 4W per core (HPC example) • Off-chip bandwidth as high as 200+ Gbps

System Drivers – So Many ? • Fabs will be filled primarily by 2-3 major applications Fabrics MPU PE/DSP Memory AMS Markets Consumer Stationary Consumer/ Mobile Medical Automotive Network Office/ Server A&D

System Drivers – So Many ? • Fabs will be filled primarily by 2-3 major applications • Drivers will follow suit – applications drive technology Fabrics MPU PE/DSP Memory AMS Markets Consumer Stationary Consumer/ Mobile Medical Automotive Network Office/ Server A&D

Evolution of System Drivers Inventory • Upcoming years may see a smaller list of key Drivers • As fabs consolidate, applications and drivers do so as well • All remaining applications will ride on existing technology curve

SOC-CP Model Revision • Qualitative changes in SoC-CP • Highresolution, large screen size video interface require high performance GPU • Cloud-based service over wireless connection eliminates dedicated PEs for speech, character and image recognition, dictionary, etc. • SoC-CP model • Current model: CPU + PE + Peripheral (+ RF, AMS) • Next model: CPU + GPU + Logic Block + IO Peripheral + Baseband (+ RF, AMS) Audio codec, Video codec,Security 2D/3D graphics DRAM-IF, USB, MIPI, HDMI, LVDS… Multi-band multi-protocol SDR

More Than Moore – AMS/RF “Subdriver” Several emphases in DT, DFT: System verification, Hetero systems Plan: paste high-level block model from AMS/RF -- “core model” Hope to obtain model from additional groups, market analysis E.G. WiFi/GPS/cellular/BT/NFC front-end blocks, tuner/demodulator blocks

A-Factor Updates (e.g., FinFET) • Ongoing for 2013 revision • Initial draft models developed in April 2012 • Many issues to work through • Gridded layout with device grid, metal grid alignment • Dummy poly isolation • Unimportant design rules become important – e.g., gate contact to active contact spacing • SRAM devices have integral sizing, no Vt control except with Lgate biasing  challenge to maintaining SRAM A-Factor • Current densities and resistivity  CD (width) scaling of VDD, VSS traces • Comprehension of wiring loads in future designs • Specs for high-performance, low-power cell libraries

Device Model / PIDS interaction • Agreed to only one low power device in the roadmap • Removed LOP device flavor  from 3 to 2 devices • Still questioning how much CD variation can be tolerated • Should Design content change as we move toward 450 mm ? • Should Design care about node definitions ? • (foundry names vs. ITRS)

Beyond 2020 • Observation: 14 years to get beyond-CMOS idea to products • ITRS groups must start to think about and act on beyond-2020 devices and their use in design • (“technology” by itself is not a complete solution) • What will be the earliest insertions into which products? • MRAM replaces SRAM • 3D with vertical nanowires (7nm) bring BEOL interfacing challenge (and: P, N in different vs. same layers?) • Spintronics • Demands Design ITWG collaboration with PIDS, Litho, Interconnect, ERD/ERM – and expanding the scope of ITRS

Summary: 2012 Design / SysDrivers Messages Design technology continues on roadmap of low-power techniques Design ITWG still clarifying impact of new devices (FinFET A-factor) Design technology for 3D continues to spread across chapter Design technology for resilience a fundamental portion of DFM More Than Moore fabrics will require increasingly specialized DT Memory an increasingly important factor for design technology Still pushing to integrate AMS/RF on SoC/SiP despite 3D prospects System Drivers: SoC-CP revision – and will soaring applications (DTV, microservers) overhaul the driver list ? ITRS groups must think about Beyond-CMOS based products and insertion points

THANK YOU

System – Device Domain Space Systems Market requirements ICs System Demand Will drive device demand Tech requirements Chip level System level

Design + System Drivers Update Design ITWG ITRS Public Conference Hsinchu, 5 Dec 2012