Appearance-based Equivalence Checking

1. Appearance-based Equivalence Checking Speaker: Ching-Yi Huang Advisor: Chun-Yao Wang Date: 2011/02/16

2. Plan in the winter vacation • Plan list: Before Lunar New Year • CAD contest - Find papers • Research • Build up the ABC environment • Trace codes of ABC • Trace codes of DEC, Node-Merging After Lunar New Year • Coding

3. Plan in the winter vacation • 1.5 weeks before Lunar New Year • 1.0 week between Lunar New Year vacation • 1.0 weeks after Lunar New Year vacation • 0.5 week bonus! • However, two serious colds…

4. Plan in the winter vacation • Plan list: Before Lunar New Year • CAD contest - Find papers • Research • Build up the ABC environment • Trace codes of ABC • Trace codes of DEC, Node-Merging • Manuscript of TCAD (A Formal Approach to Error Injection-based Rewiring Technique ) After Lunar New Year • Coding • Discuss the CAD contest

5. Outline • About ABC • Program flow • New program flow • Future work

6. About ABC • ABC = A System for Sequential Synthesis and Verification • Author:BerkeleyLogic Synthesis and Verification Group • http://www.eecs.berkeley.edu/~alanmi/abc/

7. About ABC • Similar to SIS, VIS, MVSIS • Input file: binary BLIF, binary PLA, BENCH format, a subset of EDIF (for reading ISCAS benchmarks), a subset of Synopsys equation format, and a subset of structural Verilog (for reading IWLS 2005 benchmarks) • Data Structure: BDDs, SOPs, AIG • Output file: binary BLIF (both technology-independent and mapped), binary PLA (collapsed networks only), BENCH format, Synopsys equation format, CNF (combinational miters only), and two representations for circuit graphs: DOT format (used in the graph visualization package GraphViz) and GML format (used by some graph editors, such as yEd, a free product of yWorks).

8. About ABC - files • Eqn format INORDER = a b c d e f g h i j k l; OUTORDER = o1 o2; o1 = g3*!g6; g3 = g8 + g7; • Blif format (Berkeley Logic Interchange Format (BLIF)) .model test1.eqn .inputs a b c d e f g h i j k l .outputs o1 o2 .names g3 g6 o1 10 1 .names g3 g6 g4 o2 111 1 .names g7 g8 g3 1- 1 -1 1

9. About ABC - AIG • AIG = AND-Inverter Graph • A specialized format BAF (Binary Aig Format) for reading/writing large AIGs into binary files • DAG = Direct Acyclic Graph • Two Inputs AND gate node • Inverter on the edge

10. About ABC – AIG example B C F A

11. About ABC – use ABC • Two methods: After building up the ABC environment • Call command • Ex: sprintf( Command, "print_stats" ); Cmd_CommandExecute( pAbc, Command ) • Include header file and use the data structure and functions • Ex: void Abc_ObjPatchFanin( Abc_Obj_t * pObj, Abc_Obj_t * pFaninOld, Abc_Obj_t * pFaninNew )

12. About ABC - features • Strong data structure • Great coding style – • Fast run time • Effectively use memory • Realize C++ • Ex: vector, #define for interator

13. Outline • About ABC • Program flow • New program flow • Future work

14. Flow of DEC Read .blif File Choose target wire Model the error of removing 1.Fault-activation 2.Fault-propagation Choose candidate destination Set MAs Rectification Remove target wire Reports

15. Flow of DEC (details) • Read .blif file • For all wires (as target wire) • Restructure • Testwire • Find TFO cone • Fault-activation • Find destination candidates • Fault-propagation • Choose one candidate (random) • …

16. Flow of DEC (details) • If the target has no branch • 1.SetNonBranchMA (recursive set the assignments of the side inputs) • If the MAs conflict (redundant wire) • Directly remove wire • If the MAs don’t conflict & destination is on the output of target node • AND Essential-MA (AND(TA)) to construct EAN & ERN (DON & DOFF) • Condition rectification(AND/OR) • Remove wire • If the MAs don’t conflict & destination is not the output of target node • AND Essential-MA (AND(TA)) to construct EAN & ERN (DON & DOFF) • Condition rectification(AND/OR) • Remove wire • If the target has branches • AND Essential-MA (AND(TA)) to construct EAN & ERN (DON & DOFF) • Condition rectification(AND/OR) • Remove wire

17. Flow of DEC • Problems: • 1. Only removing • 2. Only use the target node output as the destination gate

18. Outline • About ABC • Program flow • New program flow • Future work

19. New flow of my work

20. Flow of DEC Read .blif File Choose target wire Model the error of removing 1.Fault-activation 2.Fault-propagation Choose candidate destination Set MAs Rectification Remove target wire Reports

21. New flow Read .blif File Choose destination candidatesthat not only at the gate output Reports Choose target wire Options that 1.Can remove 2.Can add 3.Can replace and model the errors Set MAs Rectification Remove / Add / Replace Fault-activation Fault-propagation

22. Model the errors

23. Model the errors (AIG format) • Remove wire

24. Model the errors (AIG format) • Add wire

25. Model the errors (AIG format) • Add wire ( a with no inverter)

26. Model the errors (AIG format) • Add wire ( a with an inverter)

27. Model the errors (AIG format) • Replacement

28. Model the errors (AIG format) • Replacement

29. Model the errors (AIG format) • Only change inverter ? • Use gate replacement!

30. Future work Read .blif File Choose destination candidatesthat not only at the gate output Reports Choose target wire Options that 1.Can remove 2.Can add 3.Can replace and model the errors Set MAs Rectification Remove / Add / Replace Fault-activation Fault-propagation

31. Future work • Coding style • Reprogramming • Flow followed by Daw-Ming • Coding style learned from Yung-Chi • ICCAD’s calling for papers in April