Combinational Equivalence Checking Using Probability Techniques
In this presentation, we explore a novel approach for verifying the equivalence of two circuits, f and g, through combinational equivalence checking. Our method involves reducing fan-out in circuits and transforming them into tree structures without altering their equivalency. By implementing aliasing-free probability assignments, we manage circuit complexity and improve the efficiency of equivalence checking. Future work focuses on optimizing our approach and addressing current limitations. Join us as we dive into the methodology and implications of our findings.
Combinational Equivalence Checking Using Probability Techniques
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Presentation Transcript
Combinational Equivalence Checking using probability Speaker : Chun-ChiLin Advisor : Chun-Yao Wang 2007.08.14 Department of Computer Science National Tsing Hua University, Taiwan
Outline • Introduction • Our method • Future work
Introduction • Given two circuits f and g • Check whether f and g are equivalent • Aliasing-free probability assignment a = 1/3 a = 1/3 b = 1/5 19/255 19/255 c = 1/17 b = 1/5 c = 1/17
Introduction • The number of assignmentswe can deal have a upper limit • How to reduce input • Internal tree replacement
Introduction • Ex . We can deal 3 assignments at most 1/3 a 1/15 e 1/5 b c d 1/3 a 1/15 e 1/5 b d c
Introduction • The problem is • Most of circuits have fan-out • Small or even no chance of internal tree replacement • Can not reduce input assignment
Purpose • Given two circuits f and g • Reduce fan-out, turn them into tree structure and reduce input • Functionality may change but their equivalence still hold
Outline • Introduction • Our method • Future work
Basic ideas • Two circuits are f and g • Eliminate a fan-out from f, this new circuit is called f’ • Find f’ – f : exact add cubes, exact remove cubes • We add or remove these cubes ong and get g’ • Fan-out free recognition on g’
b c ¬b c Add cubes • Add some cubes to eliminate a fan-out • Make sure we can eliminate fan-out • ab + a¬b = a • From a circuit view ab + bc → ab + c We add cube ¬bc a b X c
b c ¬b c Removecubes • Remove some cubes to eliminate a fan-out • Make sure we can eliminate fan-out • (a+b)(a+¬b) = a • From a circuit view b + ac → bc + ac We remove cube b¬c a b X c
Exact cubes • Def: exact add cubes – cubes which original circuit doesn’t contain • Def: exact removal cubes – cubes which original circuit mustcontain
Find exact cubes • If we add(remove) non-exact cubes to(from) g, may violate their equivalence ‘ f ‘ g 1 1 add this cube add this cube Not equivalent becomes equivalent
Exact network • We use a network contain these cubes • Exact add network (EAN) – contain all exact add cubes • Exact removal network (ERN) – contain all exact add cubes
Find exact network f a EAN=a’b (fa’b)’ f’a’b … b … ERN=a’b fa’b (f’a’b )’ f’ a … b …
Exact network check • We have to check the relation between g EAN, ERN • g can not contain EAN • g must have ERN
Exact network check s-a-0 test g If testable g != f EAN If untestable g don’t contain EAN g g’ EAN
Exact network check s-a-1 test g If testable g != f ERN If untestable g haveERN g g’ ERN
Recognition on g • ga’ → b disappear? → b testable? and gb’ → a disappear? → a testable? • Then, replace a and b into another input f a b …
Flow chart Over assignment? f and g Choose a fan-out line to eliminate from f Equivalence checking using probability N Find exact network Result Reduce one input Is g conflict with exact network N Fan-out free recognition on g N Is the node tree add exact network on g Y
Current problem • g become bigger and bigger, s-a-f test become slower • How to reduce g’s size efficiently
Outline • Introduction • Our method • Future work
Future work • Solve the problems • Keep coding and debugging
