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Combinational Equivalence Checking using probability

Combinational Equivalence Checking using probability. Speaker : Chun-Chi Lin Advisor : Chun-Yao Wang 2007.08.14 Department of Computer Science National Tsing Hua University, Taiwan. Outline. Introduction Our method Future work. Introduction. Given two circuits f and g

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Combinational Equivalence Checking using probability

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  1. Combinational Equivalence Checking using probability Speaker : Chun-ChiLin Advisor : Chun-Yao Wang 2007.08.14 Department of Computer Science National Tsing Hua University, Taiwan

  2. Outline • Introduction • Our method • Future work

  3. Introduction • Given two circuits f and g • Check whether f and g are equivalent • Aliasing-free probability assignment a = 1/3 a = 1/3 b = 1/5 19/255 19/255 c = 1/17 b = 1/5 c = 1/17

  4. Introduction • The number of assignmentswe can deal have a upper limit • How to reduce input • Internal tree replacement

  5. Introduction • Ex . We can deal 3 assignments at most 1/3 a 1/15 e 1/5 b c d 1/3 a 1/15 e 1/5 b d c

  6. Introduction • The problem is • Most of circuits have fan-out • Small or even no chance of internal tree replacement • Can not reduce input assignment

  7. Purpose • Given two circuits f and g • Reduce fan-out, turn them into tree structure and reduce input • Functionality may change but their equivalence still hold

  8. Outline • Introduction • Our method • Future work

  9. Basic ideas • Two circuits are f and g • Eliminate a fan-out from f, this new circuit is called f’ • Find f’ – f : exact add cubes, exact remove cubes • We add or remove these cubes ong and get g’ • Fan-out free recognition on g’

  10. b c ¬b c Add cubes • Add some cubes to eliminate a fan-out • Make sure we can eliminate fan-out • ab + a¬b = a • From a circuit view ab + bc → ab + c We add cube ¬bc a b X c

  11. b c ¬b c Removecubes • Remove some cubes to eliminate a fan-out • Make sure we can eliminate fan-out • (a+b)(a+¬b) = a • From a circuit view b + ac → bc + ac We remove cube b¬c a b X c

  12. Exact cubes • Def: exact add cubes – cubes which original circuit doesn’t contain • Def: exact removal cubes – cubes which original circuit mustcontain

  13. Find exact cubes • If we add(remove) non-exact cubes to(from) g, may violate their equivalence ‘ f ‘ g 1 1 add this cube add this cube Not equivalent becomes equivalent

  14. Exact network • We use a network contain these cubes • Exact add network (EAN) – contain all exact add cubes • Exact removal network (ERN) – contain all exact add cubes

  15. Find exact network f a EAN=a’b (fa’b)’ f’a’b … b … ERN=a’b fa’b (f’a’b )’ f’ a … b …

  16. Exact network check • We have to check the relation between g EAN, ERN • g can not contain EAN • g must have ERN

  17. Exact network check s-a-0 test g If testable g != f EAN If untestable g don’t contain EAN g g’ EAN

  18. Exact network check s-a-1 test g If testable g != f ERN If untestable g haveERN g g’ ERN

  19. Recognition on g • ga’ → b disappear? → b testable? and gb’ → a disappear? → a testable? • Then, replace a and b into another input f a b …

  20. Flow chart Over assignment? f and g Choose a fan-out line to eliminate from f Equivalence checking using probability N Find exact network Result Reduce one input Is g conflict with exact network N Fan-out free recognition on g N Is the node tree add exact network on g Y

  21. Current problem • g become bigger and bigger, s-a-f test become slower • How to reduce g’s size efficiently

  22. Outline • Introduction • Our method • Future work

  23. Future work • Solve the problems • Keep coding and debugging

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