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Happenings

Happenings. Lots of bureaucratic stuff Creating short list for USCMS program manager & deputy Costing of the CSC upgrades Creating agenda for general muon meeting “long-range upgrades” next Monday Forward toroids ? Muon tagging to rapidity 5? Etc. Updated bad board count:

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Happenings

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  1. Happenings • Lots of bureaucratic stuff • Creating short list for USCMS program manager & deputy • Costing of the CSC upgrades • Creating agenda for general muon meeting “long-range upgrades” next Monday • Forward toroids? Muon tagging to rapidity 5? Etc. • Updated bad board count: • At B904 there are 28 bad TMB, 10 prototype TMB (trash? Save for parts?) • Also 5 bad ALCT672, 6 bad ALCT288 • Send them all back to UCLA for repair?

  2. Happenings • GEM demonstrator • In LS1, install 2 chambers GE1/1. •  Lever arm in 1/1 station increased 2.5-5.0x •  Resolution allowed by current 16:1 ganging for trigger is ~8 mrad, need at least 4x finer (see below) for trigger Full Geant Simulation Df(CSC-GEM)~ 3 mrad Dx ~6 mm pT=20 GeV pT=5 GeV

  3. List of 12 OTMB mezz problems • Went over list with Gilmore, some resolved • 1, 3: Problems loading from Eprom and time variations: mezz and base board resistor pull-ups fighting pull-downs on signal DMB_TX33 and DMB_TX{14 or 40}. • 2, 5: Clock choice: 4 new boards choose slave vs. master by choice of resistor • 9: system monitor internal ADC ground connection • Will fix • 11: agreed to add test points or labeled pads

  4. OTMB mezz problems not resolved • 4: claimed we are stuck with clunky loading of PROMs. • 6: hot-running FPGAs: claimed 85 C “normal”, max. spec. is 100 C, failure at 125 C. Safety features: • Can turn on internal FPGA shutoff when adjustable max reached… but not done… • TMB critical temperature sensor likewise… but not done… • Interlock through DCS software to shut off power… but not done • 12: board is too big – nothing to be done. • However, maybe could add smaller extractor screws

  5. OTMB mezz problems: not clear what will happen • 7: suggest bigger heat sink and/or use 10A CRB-type regulators? • 8: some signals can be moved, but he tried to optimize routing FPGA – level translator – connector, keeping to 12-layer PC board • 10: they made TMB base board mods to allow loopback testing, including making some chips 2.5v instead of 3.3v on TMB base board near the backplane • Ugh?

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