1 / 2

PHASE NOISE OF A Int -N PLL SYNTHESIZER

NOISE REDUCTION BY LOOP. PLL NOISE. TOTAL NOISE. VCO NOISE. 20Log(N/R). REF NOISE. Ref Noise. LOG SCALE. LOG SCALE. PHASE NOISE OF A Int -N PLL SYNTHESIZER. Noise Contributors in a Frac-N PLL. Example: 3 rd order MASH SD modulator, 3 rd order loop. “synth” noise. Ref. noise.

arnav
Télécharger la présentation

PHASE NOISE OF A Int -N PLL SYNTHESIZER

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. NOISE REDUCTION BY LOOP PLL NOISE TOTAL NOISE VCO NOISE 20Log(N/R) REF NOISE Ref Noise LOG SCALE LOG SCALE PHASE NOISE OF A Int-N PLL SYNTHESIZER

  2. Noise Contributors in a Frac-N PLL Example: 3rd order MASH SD modulator, 3rd order loop “synth” noise Ref. noise VCO noise 20log(N/R) 20logN SD Noise Xtal Ref. Phase Noise PFD Noise floor = FOM+10log(fPFD) • To ensure far out noise is dominated by VCO performance… • SD modulator should have sufficient OSR (power penalty) • Pole at 1/R3C3 as low as possible (trade-off vs. loop stability margin)

More Related