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DSP Final Project Proposal

DSP Final Project Proposal. 資工碩一 R95922025 吳東潤. 動機. Wireless 有關的產品越來越受歡迎與普及 Communication 中接收端如何將接收到訊號還原成原本的數位訊號 鎖相迴路 (Phase locked loop, PLL) 有不少使用離散也就是 DSP 的方法來達成再加上其被應用的領域廣泛 . PLL 系統簡介 (1). Phase detector ：計算 input 訊號與 feedback 訊號的相位差 Loop filter ： 相當與 low-pass filter 的特性

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DSP Final Project Proposal

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  1. DSP Final Project Proposal 資工碩一 R95922025 吳東潤

  2. 動機 • Wireless有關的產品越來越受歡迎與普及 • Communication中接收端如何將接收到訊號還原成原本的數位訊號 • 鎖相迴路(Phase locked loop, PLL)有不少使用離散也就是DSP的方法來達成再加上其被應用的領域廣泛

  3. PLL系統簡介(1) • Phase detector：計算input訊號與feedback訊號的相位差 • Loop filter： 相當與low-pass filter的特性 • VCO(Voltage Controlled Oscillator): 依據loop filter的相位差輸出做調整

  4. PLL系統簡介(1)

  5. 實現方法 • Input訊號將會找一組數位訊號資料，然後將其與一弦波(載波)做調變(modulation)，再加上一些高斯雜訊以模擬接收端的干擾雜訊， • 將其當input給欲所設計的PLL系統處理，再透過其找出之phase還原成數位訊號。 • PLL系統即由參考paper之定義實作

  6. 預期困難 • 涉及通訊與控制方面的知識會較難理解

  7. Reference • “Introduction to phase-lock loop system modeling”, Wen Li, senior system engineer, advanced analog product group and Jason Meiners, Design Manager, Mixed-signal product group, Texas Instruments Incorporated. • ”Pase-Locked Loops: A Control Centric Turtorial”, Danny Abramovitch Agilent Labs,3500 Deer Creek Road,MS:25U-9 Palo Alto, CA 94305-1392

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