1 / 15

Reconfigurable DSP Project

Reconfigurable DSP Project. The ChooChoo: Final Design Review Wody-Instruction Set Architecture School of Electrical and Computer Engineering Georgia Institute of Technology. MPEG II Decoder. Team Members. Walter Huang Omur Kirikci Dae-Ik Kim Ying-Chieh Ko. Problem Statement (1).

hanley
Télécharger la présentation

Reconfigurable DSP Project

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. Reconfigurable DSP Project The ChooChoo: Final Design Review Wody-Instruction Set Architecture School of Electrical and Computer Engineering Georgia Institute of Technology MPEG II Decoder FDR--ECE6276 Class Project 12/06/00

  2. Team Members • Walter Huang • Omur Kirikci • Dae-Ik Kim • Ying-Chieh Ko FDR--ECE6276 Class Project 12/06/00

  3. Problem Statement (1) • Design of ISA’s for different profiles of a reconfigurable DSP • Three Profiles IDCT, Inverse Qunatization & ZigZag and Motion Coompensation • The design of optimal ISA’s is required for each profile according to the algorithms and the architectures provided. FDR--ECE6276 Class Project 12/06/00

  4. Problem Statement (2) • Support designing and testing of entire process concerning ISA • Cooperation with other groups to support the design and testing of decoder and outlined algorithm for each profile. FDR--ECE6276 Class Project 12/06/00

  5. Requirements ISA design choices • Number of Instructions • Parallelism & Reflection of algorithm • Simplicity and coherency of instruction format between different profiles • Coherence with the proposed architecture FDR--ECE6276 Class Project 12/06/00

  6. Schedule • Regroup Modules into Profiles - 11/3 • Create ISA for Profiles – 11/6 • Create Mission Statement and Mission Plan - 11/10 • Prepare for Preliminary Design Review - 11/15 • Modify ISA for Each Profile - 11/18 • Create Small Test Program in Assembly for Each Profile - 11/19 • Verify Functionality of ISA – 11/22 • Create and Maintain Website - 11/29 • Critical Design Review - 11/29 • Final Design Review – 12/6 • Final Report – 12/6 FDR--ECE6276 Class Project 12/06/00

  7. Task distribution and organization • Walter Huang : All tasks minus website, Group leader • Omur KIRIKCI: All tasks minus testing and website • Daeik Kim : All tasks minus website • Ying-Chieh Ko : All tasks minus testing FDR--ECE6276 Class Project 12/06/00

  8. Outline of ISA’s • Each ISA is 32bit long • 6 bit opcode • 5 bit operands for supporting 31 registers(excluding R0, which is always ‘0’). • Similar to the ISA of DLX or MIPS. • First bit of opcode determines parallel or sequential execution. • Coherence of ISA’s for each profile for fast prototyping of instruction decoders. FDR--ECE6276 Class Project 12/06/00

  9. Advantages of ISA Chosen • Instructions have fixed length for ease of decoding • Supports parallel operations • All ISA’s have much similarity for rapid prototyping FDR--ECE6276 Class Project 12/06/00

  10. Limitations of ISA Chosen • No fancy memory operations • Parallel instruction make compiling more difficult with a modified RISC (DLX) compiler FDR--ECE6276 Class Project 12/06/00

  11. Support role • Make contributions to the testing of decoder design • Provide help for the simple algorithm test • Take role in adopting re-targetable assembler. FDR--ECE6276 Class Project 12/06/00

  12. Tests & results • According to the pseudo codes the Algorithm Group provided, the assembly codes are generated. • The inputs are fed according to the assembly code and the output results turned out to be satisfactory according to the expectations. FDR--ECE6276 Class Project 12/06/00

  13. Lessons learned (1) • Schedule keeping • The ISA – one of the early stages of the entire process, so high risk! • ISA is prepared on time • Technical challenges • Risk due to the possible failures or mistakes in the ISA that might affect the whole design process. • Inefficiency in ISA after the changes introduced according to the requirements. e.g. - Abandoned parallelism in profile 1 & 2 - Register swapping problem in profile 1 & 2 FDR--ECE6276 Class Project 12/06/00

  14. Lessons learned (2) • Cooperation with other teams • Responsibility of working in groups • The Role of Communication in group works • Experience of keeping the tasks done according to the specified deadlines FDR--ECE6276 Class Project 12/06/00

  15. Improvements & Suggestions • Communication channel • Reduce amount of excessive e-mails • Team specific email groups should be used since the beginning of the project FDR--ECE6276 Class Project 12/06/00

More Related