Microprocessor and Microcontrollers ( CSE-3501 ) Lecture-10

1. Microprocessor and Microcontrollers (CSE-3501)Lecture-10 Instructor: SazidZaman Khan Lecturer, Department of Computer Science and Engineering, IIUC

2. Instruction cycle • The CPU executes a program that is stored as a sequence of machine language instructions in main memory. • Therefore, the CPU fetches or brings an instruction from memory, decodes it and executes it. This is called fetch-decode-execute cycle. • However, to ensure that the execution proceeds smoothly, it is is also necessary to synchronize the activities of the processor. To keep the events synchronized, the clock located within the CPU control unit is used. This produces regular pulses on the system bus at a specific frequency, so that each pulse is an equal time following the last. This clock pulse frequency is linked to the clock speed of the processor - the higher the clock speed, the shorter the time between pulses. • Actions only occur when a pulse is detected, so that commands can be kept in time with each other across the whole computer unit.

3. Instruction cycle • The instruction execution cycle can be clearly divided into three different parts, which will now be looked at in more detail. • Fetch cycleDuring this cycle, the instruction is fetched from memory. • Decode cycleHere, the control unit checks the brought instruction that is now stored within the Instruction register. It determines which opcode and addressing mode have been used, and what actions need to be carried out in order to execute the instruction. • Execute cycleDuring this cycle the execution of the instruction is carried out.

4. Instruction cycle

5. Fetch cycle • See and note the animation from eastaughs.fsnet.co.uk (http://www.eastaughs.fsnet.co.uk/cpu/execution-fetch.htm).

6. Decode/Execute cycle • Once the instruction has been fetched and is stored, the next step is to decode the instruction in order to work out what actions should be performed to execute it. This involves examining the opcode to see which of the machine codes in the CPU's instruction set it corresponds to, and also checking which addressing mode needs to be used to obtain any required data.

7. Decode/Execute cycle • Once the opcode is known, the execution cycle can occur. Different actions need to be carried out dependant on the opcode, with no two opcodes requiring the same actions to occur. However, there are generally four groups of different actions that can occur: • Transfer of data between the CPU and memory. • Transfer of data between the CPU and an input or output devices. • Processing of data, possibly involving the use of the Arithmetic and Logic unit . • For greater simplicity, and as describing all the possible instructions is unnecessary, the following tutorial pages will only look at a few possible instructions. For example: MOV/ADD.

8. Decode/Execute cycle with immediate addressing • With immediate addressing, no lookup of data is actually required. The data is located within the operands of the instruction itself, not in a separate memory location. This is the quickest of the addressing modes to execute, but the least flexible.

9. Decode/Execute cycle with immediate addressing • See the animation from eastaughs.fsnet.co.uk (http://www.eastaughs.fsnet.co.uk/cpu/execution-immediate.htm).

10. Decode/Execute cycle with direct addressing • For direct addressing, the operands of the instruction contain the memory address where the data required for execution is stored. For the instruction to be processed the required data must be first fetched from that location. • See http://www.eastaughs.fsnet.co.uk/cpu/execution-direct.htm

11. Decode/Execute cycle with Indirect addressing • See the animation from eastaughs.fsnet.co.uk (http://www.eastaughs.fsnet.co.uk/cpu/execution-indirect.htm).